#include <synthesisEngine.hpp>
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| | CadicalEngine (Vec_Wrd_t *vSimsIn, Vec_Wrd_t *vSimsOut, int nIns, int nDivs, int nOuts, int nNodes, const std::unordered_map< int, std::unordered_set< int > > &forbidden_pairs, eSLIMLog &log, const eSLIMConfig &cfg) |
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| Mini_Aig_t * | getCircuit (int size, double timeout) |
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Definition at line 91 of file synthesisEngine.hpp.
◆ CadicalEngine()
| eSLIM::CadicalEngine::CadicalEngine |
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Vec_Wrd_t * | vSimsIn, |
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Vec_Wrd_t * | vSimsOut, |
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int | nIns, |
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int | nDivs, |
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int | nOuts, |
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int | nNodes, |
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const std::unordered_map< int, std::unordered_set< int > > & | forbidden_pairs, |
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eSLIMLog & | log, |
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const eSLIMConfig & | cfg ) |
◆ getCircuit()
| Mini_Aig_t * eSLIM::CadicalEngine::getCircuit |
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int | size, |
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double | timeout ) |
The documentation for this class was generated from the following file: