ABC: A System for Sequential Synthesis and Verification
 
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eSLIMMan.hpp
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1
20
21#ifndef ABC__OPT__ESLIM__ESLIMMAN_h
22#define ABC__OPT__ESLIM__ESLIMMAN_h
23
24#include <vector>
25#include <unordered_map>
26#include <unordered_set>
27
29#include "misc/vec/vec.h"
30#include "aig/gia/gia.h"
31#include "misc/util/utilTruth.h" // ioResub.h depends on utilTruth.h
32#include "base/io/ioResub.h"
33#include "aig/miniaig/miniaig.h"
34
35#include "utils.hpp"
36#include "selectionStrategy.hpp"
37
38
40
41namespace eSLIM {
42
43 template<class SynthesisEngine, class RelationEngine, class SelectionEngine>
44 class eSLIM_Man {
45
46 public:
47 static Gia_Man_t* applyeSLIM(Gia_Man_t * p, const eSLIMConfig& cfg, eSLIMLog& log);
48 private:
49
50 eSLIM_Man(Gia_Man_t * gia_man, const eSLIMConfig& cfg, eSLIMLog& log);
51 Gia_Man_t* getCircuit();
52
53 void minimize();
54 void findReplacement();
55 Mini_Aig_t* findMinimumAig(const Subcircuit& subcir);
56
57 Vec_Wrd_t* getSimsIn(Abc_RData_t* relation);
58 Vec_Wrd_t* getSimsOut(Abc_RData_t* relation);
59 word getAllFalseBehaviour(const Subcircuit& subcir);
60 bool getAllFalseBehaviourRec(Gia_Obj_t * pObj);
61
62 std::pair<int, Mini_Aig_t*> reduce( Vec_Wrd_t* vSimsDiv, Vec_Wrd_t* vSimsOut, const std::unordered_map<int, std::unordered_set<int>>& forbidden_pairs,
63 int nVars, int nDivs, int nOuts, int initial_size);
64 Mini_Aig_t* computeReplacement( SynthesisEngine& syn_man, int size);
65 double getDynamicTimeout(int size);
66
67 void insertReplacement(Mini_Aig_t* replacement, const Subcircuit& subcir);
68 std::vector<int> processReplacement(Gia_Man_t* gia_man, Gia_Man_t* pNew, const Subcircuit& subcir, Mini_Aig_t* replacement, std::vector<int>&& to_process, std::vector<int>& replacement_values);
69 Vec_Int_t * processEncompassing(Gia_Man_t* gia_man, Gia_Man_t* pNew, Vec_Int_t* to_process);
70 int getInsertionLiteral(Gia_Man_t* gia_man, const Subcircuit& subcir, Mini_Aig_t* replacement, const std::vector<int>& replacement_values, int fanin_lit);
71
72 Gia_Man_t* gia_man = nullptr;
73 const eSLIMConfig& cfg;
74 eSLIMLog& log;
75 SelectionEngine subcircuit_selection;
76
77 double relation_generation_time ;
78 double synthesis_time ;
79
80 bool stopeSLIM=false;
81
82 };
83
84 template <typename Y, typename R, typename S>
85 inline Gia_Man_t* eSLIM_Man<Y, R, S>::getCircuit() {
86 return gia_man;
87 }
88}
89
91
92#include "eSLIMMan.tpp"
93
94#endif
#define ABC_NAMESPACE_CXX_HEADER_START
#define ABC_NAMESPACE_CXX_HEADER_END
typedefABC_NAMESPACE_IMPL_START struct Vec_Int_t_ Vec_Int_t
DECLARATIONS ///.
Definition bblif.c:37
static Gia_Man_t * applyeSLIM(Gia_Man_t *p, const eSLIMConfig &cfg, eSLIMLog &log)
pcover reduce()
Cube * p
Definition exorList.c:222
struct Gia_Obj_t_ Gia_Obj_t
Definition gia.h:76
struct Gia_Man_t_ Gia_Man_t
Definition gia.h:96
typedefABC_NAMESPACE_HEADER_START struct Abc_RData_t_ Abc_RData_t
INCLUDES ///.
Definition ioResub.h:40
unsigned __int64 word
DECLARATIONS ///.
Definition kitPerm.c:36
struct Mini_Aig_t_ Mini_Aig_t
BASIC TYPES ///.
Definition miniaig.h:48
typedefABC_NAMESPACE_HEADER_START struct Vec_Wrd_t_ Vec_Wrd_t
INCLUDES ///.
Definition vecWrd.h:42