abcFpgaFast.c File Reference

#include "base/abc/abc.h"
#include "aig/ivy/ivy.h"

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Functions
ABC_NAMESPACE_IMPL_START Ivy_Man_t *	Abc_NtkIvyBefore (Abc_Ntk_t *pNtk, int fSeq, int fUseDc)
	DECLARATIONS ///.
Abc_Ntk_t *	Abc_NtkFpgaFast (Abc_Ntk_t *pNtk, int nLutSize, int fRecovery, int fVerbose)
	FUNCTION DEFINITIONS ///.

Function Documentation

Abc_NtkFpgaFast()

Abc_Ntk_t * Abc_NtkFpgaFast	(	Abc_Ntk_t *	pNtk,
		int	nLutSize,
		int	fRecovery,
		int	fVerbose )

FUNCTION DEFINITIONS ///.

Function*************************************************************

Synopsis [Performs fast FPGA mapping of the network.]

Description [Takes the AIG to be mapped, the LUT size, and verbosity flag. Produces the new network by fast FPGA mapping of the current network. If the current network in ABC in not an AIG, the user should run command "strash" to make sure that the current network into an AIG before calling this procedure.]

SideEffects []

SeeAlso []

Definition at line 58 of file abcFpgaFast.c.

{
    Ivy_Man_t * pMan;
    Abc_Ntk_t * pNtkNew;
    // make sure the network is an AIG
    assert( Abc_NtkIsStrash(pNtk) );
    // convert the network into the AIG
    pMan = Abc_NtkIvyBefore( pNtk, 0, 0 );
    // perform fast FPGA mapping
    Ivy_FastMapPerform( pMan, nLutSize, fRecovery, fVerbose );
    // convert back into the ABC network
    pNtkNew = Ivy_ManFpgaToAbc( pNtk, pMan );
    Ivy_FastMapStop( pMan );
    Ivy_ManStop( pMan );  
    // make sure that the final network passes the test
    if ( pNtkNew != NULL && !Abc_NtkCheck( pNtkNew ) )
    {
        printf( "Abc_NtkFastMap: The network check has failed.\n" );
        Abc_NtkDelete( pNtkNew );
        return NULL;
    }
    return pNtkNew;
}

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Abc_NtkIvyBefore()

ABC_NAMESPACE_IMPL_START Ivy_Man_t * Abc_NtkIvyBefore ( Abc_Ntk_t * pNtk, int fSeq, int fUseDc )

extern

DECLARATIONS ///.

CFile****************************************************************

FileName [abcFpgaFast.c]

SystemName [ABC: Logic synthesis and verification system.]

PackageName [Network and node package.]

Synopsis [Fast FPGA mapper.]

Author [Sungmin Cho]

Affiliation [UC Berkeley]

Date [Ver. 1.0. Started - June 20, 2005.]

Revision [

Id

abcFpgaFast.c,v 1.00 2006/09/02 00:00:00 alanmi Exp

]

DECLARATIONS ///.

Function*************************************************************

Synopsis [Prepares the IVY package.]

Description []

SideEffects []

SeeAlso []

Definition at line 88 of file abcIvy.c.

{
    Ivy_Man_t * pMan;
//timeRetime = Abc_Clock();
    assert( !Abc_NtkIsNetlist(pNtk) );
    if ( Abc_NtkIsBddLogic(pNtk) )
    {
        if ( !Abc_NtkBddToSop(pNtk, -1, ABC_INFINITY, 1) )
        {
            printf( "Abc_NtkIvyBefore(): Converting to SOPs has failed.\n" );
            return NULL;
        }
    }
    if ( fSeq && Abc_NtkCountSelfFeedLatches(pNtk) )
    {
        printf( "Warning: The network has %d self-feeding latches.\n", Abc_NtkCountSelfFeedLatches(pNtk) );
//        return NULL;
    }
    // print warning about choice nodes
    if ( Abc_NtkGetChoiceNum( pNtk ) )
        printf( "Warning: The choice nodes in the initial AIG are removed by strashing.\n" );
    // convert to the AIG manager
    pMan = Abc_NtkToIvy( pNtk );
    if ( !Ivy_ManCheck( pMan ) )
    {
        printf( "AIG check has failed.\n" );
        Ivy_ManStop( pMan );
        return NULL;
    }
//    Ivy_ManPrintStats( pMan );
    if ( fSeq )
    {
        int nLatches = Abc_NtkLatchNum(pNtk);
        Vec_Int_t * vInit = Abc_NtkCollectLatchValuesIvy( pNtk, fUseDc );
        Ivy_ManMakeSeq( pMan, nLatches, vInit->pArray );
        Vec_IntFree( vInit );
//        Ivy_ManPrintStats( pMan );
    }
//timeRetime = Abc_Clock() - timeRetime;
    return pMan;
}

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