ABC: A System for Sequential Synthesis and Verification
 
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bacWriteVer.c
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1
20
21#include "bac.h"
22#include "bacPrs.h"
23#include "map/mio/mio.h"
24#include "base/main/main.h"
25
27
31
35
47static void Psr_ManWriteVerilogConcat( FILE * pFile, Psr_Ntk_t * p, int Con )
48{
49 extern void Psr_ManWriteVerilogArray( FILE * pFile, Psr_Ntk_t * p, Vec_Int_t * vSigs, int Start, int Stop, int fOdd );
50 Vec_Int_t * vSigs = Psr_CatSignals(p, Con);
51 fprintf( pFile, "{" );
52 Psr_ManWriteVerilogArray( pFile, p, vSigs, 0, Vec_IntSize(vSigs), 0 );
53 fprintf( pFile, "}" );
54}
55static void Psr_ManWriteVerilogSignal( FILE * pFile, Psr_Ntk_t * p, int Sig )
56{
57 int Value = Abc_Lit2Var2( Sig );
58 Psr_ManType_t Type = (Psr_ManType_t)Abc_Lit2Att2( Sig );
59 if ( Type == BAC_PRS_NAME || Type == BAC_PRS_CONST )
60 fprintf( pFile, "%s", Psr_NtkStr(p, Value) );
61 else if ( Type == BAC_PRS_SLICE )
62 fprintf( pFile, "%s%s", Psr_NtkStr(p, Psr_SliceName(p, Value)), Psr_NtkStr(p, Psr_SliceRange(p, Value)) );
63 else if ( Type == BAC_PRS_CONCAT )
64 Psr_ManWriteVerilogConcat( pFile, p, Value );
65 else assert( 0 );
66}
67void Psr_ManWriteVerilogArray( FILE * pFile, Psr_Ntk_t * p, Vec_Int_t * vSigs, int Start, int Stop, int fOdd )
68{
69 int i, Sig;
70 assert( Vec_IntSize(vSigs) > 0 );
71 Vec_IntForEachEntryStartStop( vSigs, Sig, i, Start, Stop )
72 {
73 if ( fOdd && !(i & 1) )
74 continue;
75 Psr_ManWriteVerilogSignal( pFile, p, Sig );
76 fprintf( pFile, "%s", i == Stop - 1 ? "" : ", " );
77 }
78}
79static void Psr_ManWriteVerilogArray2( FILE * pFile, Psr_Ntk_t * p, Vec_Int_t * vSigs )
80{
81 int i, FormId, ActSig;
82 assert( Vec_IntSize(vSigs) % 2 == 0 );
83 Vec_IntForEachEntryDouble( vSigs, FormId, ActSig, i )
84 {
85 fprintf( pFile, "." );
86 fprintf( pFile, "%s", Psr_NtkStr(p, FormId) );
87 fprintf( pFile, "(" );
88 Psr_ManWriteVerilogSignal( pFile, p, ActSig );
89 fprintf( pFile, ")%s", (i == Vec_IntSize(vSigs) - 2) ? "" : ", " );
90 }
91}
92static void Psr_ManWriteVerilogMux( FILE * pFile, Psr_Ntk_t * p, Vec_Int_t * vSigs )
93{
94 int i, FormId, ActSig;
95 char * pStrs[4] = { " = ", " ? ", " : ", ";\n" };
96 assert( Vec_IntSize(vSigs) == 8 );
97 fprintf( pFile, " assign " );
98 Psr_ManWriteVerilogSignal( pFile, p, Vec_IntEntryLast(vSigs) );
99 fprintf( pFile, "%s", pStrs[0] );
100 Vec_IntForEachEntryDouble( vSigs, FormId, ActSig, i )
101 {
102 Psr_ManWriteVerilogSignal( pFile, p, ActSig );
103 fprintf( pFile, "%s", pStrs[1+i/2] );
104 if ( i == 4 )
105 break;
106 }
107}
108static void Psr_ManWriteVerilogBoxes( FILE * pFile, Psr_Ntk_t * p )
109{
110 Vec_Int_t * vBox; int i;
111 Psr_NtkForEachBox( p, vBox, i )
112 {
113 Bac_ObjType_t NtkId = (Bac_ObjType_t)Psr_BoxNtk(p, i);
114 if ( NtkId == BAC_BOX_MUX )
115 Psr_ManWriteVerilogMux( pFile, p, vBox );
116 else if ( Psr_BoxIsNode(p, i) ) // node ------- check order of fanins
117 {
118 fprintf( pFile, " %s (", Ptr_TypeToName(NtkId) );
119 Psr_ManWriteVerilogSignal( pFile, p, Vec_IntEntryLast(vBox) );
120 if ( Psr_BoxIONum(p, i) > 1 )
121 fprintf( pFile, ", " );
122 Psr_ManWriteVerilogArray( pFile, p, vBox, 0, Vec_IntSize(vBox)-2, 1 );
123 fprintf( pFile, ");\n" );
124 }
125 else // box
126 {
127 //char * s = Psr_NtkStr(p, Vec_IntEntry(vBox, 0));
128 fprintf( pFile, " %s %s (", Psr_NtkStr(p, NtkId), Psr_BoxName(p, i) ? Psr_NtkStr(p, Psr_BoxName(p, i)) : "" );
129 Psr_ManWriteVerilogArray2( pFile, p, vBox );
130 fprintf( pFile, ");\n" );
131 }
132 }
133}
134static void Psr_ManWriteVerilogIos( FILE * pFile, Psr_Ntk_t * p, int SigType )
135{
136 int NameId, RangeId, i;
137 char * pSigNames[4] = { "inout", "input", "output", "wire" };
138 Vec_Int_t * vSigs[4] = { &p->vInouts, &p->vInputs, &p->vOutputs, &p->vWires };
139 Vec_Int_t * vSigsR[4] = { &p->vInoutsR, &p->vInputsR, &p->vOutputsR, &p->vWiresR };
140 if ( SigType == 3 )
141 fprintf( pFile, "\n" );
142 Vec_IntForEachEntryTwo( vSigs[SigType], vSigsR[SigType], NameId, RangeId, i )
143 fprintf( pFile, " %s %s%s;\n", pSigNames[SigType], RangeId ? Psr_NtkStr(p, RangeId) : "", Psr_NtkStr(p, NameId) );
144}
145static void Psr_ManWriteVerilogIoOrder( FILE * pFile, Psr_Ntk_t * p, Vec_Int_t * vOrder )
146{
147 int i, NameId;
148 Vec_IntForEachEntry( vOrder, NameId, i )
149 fprintf( pFile, "%s%s", Psr_NtkStr(p, NameId), i == Vec_IntSize(vOrder) - 1 ? "" : ", " );
150}
151static void Psr_ManWriteVerilogNtk( FILE * pFile, Psr_Ntk_t * p )
152{
153 int s;
154 // write header
155 fprintf( pFile, "module %s (\n ", Psr_NtkStr(p, p->iModuleName) );
156 Psr_ManWriteVerilogIoOrder( pFile, p, &p->vOrder );
157 fprintf( pFile, "\n );\n" );
158 // write declarations
159 for ( s = 0; s < 4; s++ )
160 Psr_ManWriteVerilogIos( pFile, p, s );
161 fprintf( pFile, "\n" );
162 // write objects
163 Psr_ManWriteVerilogBoxes( pFile, p );
164 fprintf( pFile, "endmodule\n\n" );
165}
166void Psr_ManWriteVerilog( char * pFileName, Vec_Ptr_t * vPrs )
167{
168 Psr_Ntk_t * pNtk = Psr_ManRoot(vPrs); int i;
169 FILE * pFile = fopen( pFileName, "wb" );
170 if ( pFile == NULL )
171 {
172 printf( "Cannot open output file \"%s\".\n", pFileName );
173 return;
174 }
175 fprintf( pFile, "// Design \"%s\" written by ABC on %s\n\n", Psr_NtkStr(pNtk, pNtk->iModuleName), Extra_TimeStamp() );
176 Vec_PtrForEachEntry( Psr_Ntk_t *, vPrs, pNtk, i )
177 Psr_ManWriteVerilogNtk( pFile, pNtk );
178 fclose( pFile );
179}
180
181
182
194// compute range of a name (different from range of a multi-bit wire)
195static inline int Bac_ObjGetRange( Bac_Ntk_t * p, int iObj )
196{
197 int i, NameId = Bac_ObjName(p, iObj);
198 assert( Bac_ObjIsCi(p, iObj) );
199// if ( Bac_NameType(NameId) == BAC_NAME_INDEX )
200// NameId = Bac_ObjName(p, iObj - Abc_Lit2Var2(NameId));
201 assert( Bac_NameType(NameId) == BAC_NAME_WORD || Bac_NameType(NameId) == BAC_NAME_INFO );
202 for ( i = iObj + 1; i < Bac_NtkObjNum(p); i++ )
203 if ( !Bac_ObjIsCi(p, i) || Bac_ObjNameType(p, i) != BAC_NAME_INDEX )
204 break;
205 return i - iObj;
206}
207
208static inline void Bac_ManWriteVar( Bac_Ntk_t * p, int RealName )
209{
210 Vec_StrPrintStr( p->pDesign->vOut, Bac_NtkStr(p, RealName) );
211}
212static inline void Bac_ManWriteRange( Bac_Ntk_t * p, int Beg, int End )
213{
214 Vec_Str_t * vStr = p->pDesign->vOut;
215 Vec_StrPrintStr( vStr, "[" );
216 if ( End >= 0 )
217 {
218 Vec_StrPrintNum( vStr, End );
219 Vec_StrPrintStr( vStr, ":" );
220 }
221 Vec_StrPrintNum( vStr, Beg );
222 Vec_StrPrintStr( vStr, "]" );
223}
224static inline void Bac_ManWriteConstBit( Bac_Ntk_t * p, int iObj, int fHead )
225{
226 Vec_Str_t * vStr = p->pDesign->vOut;
227 int Const = Bac_ObjGetConst(p, iObj);
228 assert( Const );
229 if ( fHead )
230 Vec_StrPrintStr( vStr, "1\'b" );
231 if ( Const == BAC_BOX_CF )
232 Vec_StrPush( vStr, '0' );
233 else if ( Const == BAC_BOX_CT )
234 Vec_StrPush( vStr, '1' );
235 else if ( Const == BAC_BOX_CX )
236 Vec_StrPush( vStr, 'x' );
237 else if ( Const == BAC_BOX_CZ )
238 Vec_StrPush( vStr, 'z' );
239 else assert( 0 );
240}
241static inline int Bac_ManFindRealNameId( Bac_Ntk_t * p, int iObj )
242{
243 int NameId = Bac_ObjName(p, iObj);
244 assert( Bac_ObjIsCi(p, iObj) );
245 if ( Bac_NameType(NameId) == BAC_NAME_INDEX )
246 NameId = Bac_ObjName(p, iObj - Abc_Lit2Var2(NameId));
247 if ( Bac_NameType(NameId) == BAC_NAME_INFO )
248 return Bac_NtkInfoName(p, Abc_Lit2Var2(NameId));
249 assert( Bac_NameType(NameId) == BAC_NAME_BIN || Bac_NameType(NameId) == BAC_NAME_WORD );
250 return Abc_Lit2Var2(NameId);
251}
252static inline int Bac_ManFindRealIndex( Bac_Ntk_t * p, int iObj )
253{
254 int iBit = 0, NameId = Bac_ObjName(p, iObj);
255 assert( Bac_ObjIsCi(p, iObj) );
256 assert( Bac_NameType(NameId) != BAC_NAME_BIN );
257 if ( Bac_NameType(NameId) == BAC_NAME_INDEX )
258 NameId = Bac_ObjName(p, iObj - (iBit = Abc_Lit2Var2(NameId)));
259 if ( Bac_NameType(NameId) == BAC_NAME_INFO )
260 return Bac_NtkInfoIndex(p, Abc_Lit2Var2(NameId), iBit);
261 assert( Bac_NameType(NameId) == BAC_NAME_WORD );
262 return iBit;
263}
264static inline void Bac_ManWriteSig( Bac_Ntk_t * p, int iObj )
265{
266 if ( Bac_ObjIsCo(p, iObj) )
267 iObj = Bac_ObjFanin(p, iObj);
268 assert( Bac_ObjIsCi(p, iObj) );
269 if ( Bac_ObjGetConst(p, iObj) )
270 Bac_ManWriteConstBit( p, iObj, 1 );
271 else
272 {
273 int NameId = Bac_ObjName(p, iObj);
274 if ( Bac_NameType(NameId) == BAC_NAME_BIN )
275 Bac_ManWriteVar( p, Abc_Lit2Var2(NameId) );
276 else
277 {
278 Bac_ManWriteVar( p, Bac_ManFindRealNameId(p, iObj) );
279 Bac_ManWriteRange( p, Bac_ManFindRealIndex(p, iObj), -1 );
280 }
281 }
282}
283static inline void Bac_ManWriteConcat( Bac_Ntk_t * p, int iStart, int nObjs )
284{
285 Vec_Str_t * vStr = p->pDesign->vOut;
286 assert( nObjs >= 1 );
287 if ( nObjs == 1 )
288 {
289 Bac_ManWriteSig( p, iStart );
290 return;
291 }
292 Vec_StrPrintStr( vStr, "{" );
293 if ( Bac_ObjIsBo(p, iStart) ) // box output
294 {
295 int i;
296 for ( i = iStart + nObjs - 1; i >= iStart; i-- )
297 {
298 if ( Bac_ObjNameType(p, i) == BAC_NAME_INDEX )
299 continue;
300 if ( Vec_StrEntryLast(vStr) != '{' )
301 Vec_StrPrintStr( vStr, ", " );
302 Bac_ManWriteVar( p, Bac_ManFindRealNameId(p, i) );
303 }
304 }
305 else if ( Bac_ObjIsBi(p, iStart) ) // box input
306 {
307 int e, b, k, NameId;
308 for ( e = iStart - nObjs + 1; e <= iStart; )
309 {
310 if ( Vec_StrEntryLast(vStr) != '{' )
311 Vec_StrPrintStr( vStr, ", " );
312 // write constant
313 if ( Bac_ObjGetConst(p, Bac_ObjFanin(p, e)) )
314 {
315 int fBinary = Bac_ObjIsConstBin(p, Bac_ObjFanin(p, e)-1);
316 for ( b = e + 1; b <= iStart; b++ )
317 {
318 if ( !Bac_ObjGetConst(p, Bac_ObjFanin(p, b)) )
319 break;
320 if ( !Bac_ObjIsConstBin(p, Bac_ObjFanin(p, b)-1) )
321 fBinary = 0;
322 }
323 Vec_StrPrintNum( vStr, b - e );
324 if ( fBinary && b - e > 8 ) // write hex if more than 8 bits
325 {
326 int Digit = 0, nBits = ((b - e) & 3) ? (b - e) & 3 : 4;
327 Vec_StrPrintStr( vStr, "\'h" );
328 for ( k = e; k < b; k++ )
329 {
330 Digit = 2*Digit + Bac_ObjGetConst(p, Bac_ObjFanin(p, k)) - BAC_BOX_CF;
331 assert( Digit < 16 );
332 if ( --nBits == 0 )
333 {
334 Vec_StrPush( vStr, (char)(Digit < 10 ? '0' + Digit : 'a' + Digit - 10) );
335 nBits = 4;
336 Digit = 0;
337 }
338 }
339 assert( nBits == 4 );
340 assert( Digit == 0 );
341 }
342 else
343 {
344 Vec_StrPrintStr( vStr, "\'b" );
345 for ( k = e; k < b; k++ )
346 Bac_ManWriteConstBit( p, Bac_ObjFanin(p, k), 0 );
347 }
348 e = b;
349 continue;
350 }
351 // try replication
352 for ( b = e + 1; b <= iStart; b++ )
353 if ( Bac_ObjFanin(p, b) != Bac_ObjFanin(p, e) )
354 break;
355 if ( b > e + 2 ) // more than two
356 {
357 Vec_StrPrintNum( vStr, b - e );
358 Vec_StrPrintStr( vStr, "{" );
359 Bac_ManWriteSig( p, e );
360 Vec_StrPrintStr( vStr, "}" );
361 e = b;
362 continue;
363 }
364 NameId = Bac_ObjName(p, Bac_ObjFanin(p, e));
365 if ( Bac_NameType(NameId) == BAC_NAME_BIN )
366 {
367 Bac_ManWriteVar( p, Abc_Lit2Var2(NameId) );
368 e++;
369 continue;
370 }
371 // find end of the slice
372 for ( b = e + 1; b <= iStart; b++ )
373 if ( Bac_ObjFanin(p, e) - Bac_ObjFanin(p, b) != b - e )
374 break;
375 // write signal name
376 Bac_ManWriteVar( p, Bac_ManFindRealNameId(p, Bac_ObjFanin(p, e)) );
377 if ( b == e + 1 ) // literal
378 Bac_ManWriteRange( p, Bac_ManFindRealIndex(p, Bac_ObjFanin(p, e)), -1 );
379 else // slice or complete variable
380 {
381 // consider first variable of the slice
382 int f = Bac_ObjFanin( p, b-1 );
383 assert( Bac_ObjNameType(p, f) != BAC_NAME_BIN );
384 if ( Bac_ObjNameType(p, f) == BAC_NAME_INDEX || Bac_ObjGetRange(p, f) != b - e ) // slice
385 Bac_ManWriteRange( p, Bac_ManFindRealIndex(p, f), Bac_ManFindRealIndex(p, Bac_ObjFanin(p, e)) );
386 // else this is complete variable
387 }
388 e = b;
389 }
390 }
391 else assert( 0 );
392 Vec_StrPrintStr( vStr, "}" );
393}
394static inline void Bac_ManWriteGate( Bac_Ntk_t * p, int iObj )
395{
396 Vec_Str_t * vStr = p->pDesign->vOut; int iTerm, k;
397 char * pGateName = Abc_NamStr(p->pDesign->pMods, Bac_BoxNtkId(p, iObj));
399 Mio_Gate_t * pGate = Mio_LibraryReadGateByName( pLib, pGateName, NULL );
400 Vec_StrPrintStr( vStr, " " );
401 Vec_StrPrintStr( vStr, pGateName );
402 Vec_StrPrintStr( vStr, " " );
403 Vec_StrPrintStr( vStr, Bac_ObjName(p, iObj) ? Bac_ObjNameStr(p, iObj) : "" );
404 Vec_StrPrintStr( vStr, " (" );
405 Bac_BoxForEachBi( p, iObj, iTerm, k )
406 {
407 Vec_StrPrintStr( vStr, k ? ", ." : "." );
408 Vec_StrPrintStr( vStr, Mio_GateReadPinName(pGate, k) );
409 Vec_StrPrintStr( vStr, "(" );
410 Bac_ManWriteSig( p, iTerm );
411 Vec_StrPrintStr( vStr, ")" );
412 }
413 Bac_BoxForEachBo( p, iObj, iTerm, k )
414 {
415 Vec_StrPrintStr( vStr, Bac_BoxBiNum(p, iObj) ? ", ." : "." );
416 Vec_StrPrintStr( vStr, Mio_GateReadOutName(pGate) );
417 Vec_StrPrintStr( vStr, "(" );
418 Bac_ManWriteSig( p, iTerm );
419 Vec_StrPrintStr( vStr, ")" );
420 }
421 Vec_StrPrintStr( vStr, ");\n" );
422}
423static inline void Bac_ManWriteAssign( Bac_Ntk_t * p, int iObj )
424{
425 Vec_Str_t * vStr = p->pDesign->vOut;
426 Bac_ObjType_t Type = Bac_ObjType(p, iObj);
427 int nInputs = Bac_BoxBiNum(p, iObj);
428 int nOutputs = Bac_BoxBoNum(p, iObj);
429 assert( nOutputs == 1 );
430 Vec_StrPrintStr( vStr, " assign " );
431 Bac_ManWriteSig( p, iObj + 1 );
432 Vec_StrPrintStr( vStr, " = " );
433 if ( nInputs == 0 )
434 {
435 if ( Type == BAC_BOX_CF )
436 Vec_StrPrintStr( vStr, "1\'b0" );
437 else if ( Type == BAC_BOX_CT )
438 Vec_StrPrintStr( vStr, "1\'b1" );
439 else if ( Type == BAC_BOX_CX )
440 Vec_StrPrintStr( vStr, "1\'bx" );
441 else if ( Type == BAC_BOX_CZ )
442 Vec_StrPrintStr( vStr, "1\'bz" );
443 else assert( 0 );
444 }
445 else if ( nInputs == 1 )
446 {
447 if ( Type == BAC_BOX_INV )
448 Vec_StrPrintStr( vStr, "~" );
449 else assert( Type == BAC_BOX_BUF );
450 Bac_ManWriteSig( p, iObj - 1 );
451 }
452 else if ( nInputs == 2 )
453 {
454 if ( Type == BAC_BOX_NAND || Type == BAC_BOX_NOR || Type == BAC_BOX_XNOR || Type == BAC_BOX_SHARPL )
455 Vec_StrPrintStr( vStr, "~" );
456 Bac_ManWriteSig( p, iObj - 1 );
457 if ( Type == BAC_BOX_AND || Type == BAC_BOX_SHARPL )
458 Vec_StrPrintStr( vStr, " & " );
459 else if ( Type == BAC_BOX_SHARP || Type == BAC_BOX_NOR )
460 Vec_StrPrintStr( vStr, " & ~" );
461 else if ( Type == BAC_BOX_OR )
462 Vec_StrPrintStr( vStr, " | " );
463 else if ( Type == BAC_BOX_NAND )
464 Vec_StrPrintStr( vStr, " | ~" );
465 else if ( Type == BAC_BOX_XOR || Type == BAC_BOX_XNOR )
466 Vec_StrPrintStr( vStr, " ^ " );
467 else assert( 0 );
468 Bac_ManWriteSig( p, iObj - 2 );
469 }
470 Vec_StrPrintStr( vStr, ";\n" );
471}
472void Bac_ManWriteVerilogBoxes( Bac_Ntk_t * p, int fUseAssign )
473{
474 Vec_Str_t * vStr = p->pDesign->vOut;
475 int iObj, k, i, o, StartPos;
476 Bac_NtkForEachBox( p, iObj ) // .subckt/.gate/box (formal/actual binding)
477 {
478 // skip constants
479 if ( Bac_ObjIsConst(p, iObj) )
480 continue;
481 // write mapped
482 if ( Bac_ObjIsGate(p, iObj) )
483 {
484 Bac_ManWriteGate( p, iObj );
485 continue;
486 }
487 // write primitives as assign-statements
488 if ( !Bac_ObjIsBoxUser(p, iObj) && fUseAssign )
489 {
490 Bac_ManWriteAssign( p, iObj );
491 continue;
492 }
493 // write header
494 StartPos = Vec_StrSize(vStr);
495 if ( Bac_ObjIsBoxUser(p, iObj) )
496 {
497 int Value, Beg, End, Range;
498 Bac_Ntk_t * pModel = Bac_BoxNtk( p, iObj );
499 Vec_StrPrintStr( vStr, " " );
500 Vec_StrPrintStr( vStr, Bac_NtkName(pModel) );
501 Vec_StrPrintStr( vStr, " " );
502 Vec_StrPrintStr( vStr, Bac_ObjName(p, iObj) ? Bac_ObjNameStr(p, iObj) : "" );
503 Vec_StrPrintStr( vStr, " (" );
504 // write arguments
505 i = o = 0;
506 assert( Bac_NtkInfoNum(pModel) );
507 Vec_IntForEachEntryTriple( &pModel->vInfo, Value, Beg, End, k )
508 {
509 int NameId = Abc_Lit2Var2( Value );
510 int Type = Abc_Lit2Att2( Value );
511 Vec_StrPrintStr( vStr, k ? ", " : "" );
512 if ( Vec_StrSize(vStr) > StartPos + 70 )
513 {
514 StartPos = Vec_StrSize(vStr);
515 Vec_StrPrintStr( vStr, "\n " );
516 }
517 Vec_StrPrintStr( vStr, "." );
518 Vec_StrPrintStr( vStr, Bac_NtkStr(p, NameId) );
519 Vec_StrPrintStr( vStr, "(" );
520 Range = Bac_InfoRange( Beg, End );
521 assert( Range > 0 );
522 if ( Type == 1 )
523 Bac_ManWriteConcat( p, Bac_BoxBi(p, iObj, i), Range ), i += Range;
524 else if ( Type == 2 )
525 Bac_ManWriteConcat( p, Bac_BoxBo(p, iObj, o), Range ), o += Range;
526 else assert( 0 );
527 Vec_StrPrintStr( vStr, ")" );
528 }
529 assert( i == Bac_BoxBiNum(p, iObj) );
530 assert( o == Bac_BoxBoNum(p, iObj) );
531 }
532 else
533 {
534 int iTerm, k, Range, iSig = 0;
535 Vec_Int_t * vBits = Bac_BoxCollectRanges( p, iObj );
536 char * pName = Bac_NtkGenerateName( p, Bac_ObjType(p, iObj), vBits );
537 char * pSymbs = Bac_ManPrimSymb( p->pDesign, Bac_ObjType(p, iObj) );
538 Vec_StrPrintStr( vStr, " " );
539 Vec_StrPrintStr( vStr, pName );
540 Vec_StrPrintStr( vStr, " " );
541 Vec_StrPrintStr( vStr, Bac_ObjName(p, iObj) ? Bac_ObjNameStr(p, iObj) : "" );
542 Vec_StrPrintStr( vStr, " (" );
543 // write inputs
544 Bac_BoxForEachBiMain( p, iObj, iTerm, k )
545 {
546 Range = Vec_IntEntry( vBits, iSig );
547 Vec_StrPrintStr( vStr, iSig ? ", " : "" );
548 if ( Vec_StrSize(vStr) > StartPos + 70 )
549 {
550 StartPos = Vec_StrSize(vStr);
551 Vec_StrPrintStr( vStr, "\n " );
552 }
553 Vec_StrPrintStr( vStr, "." );
554 Vec_StrPush( vStr, pSymbs[iSig] );
555 Vec_StrPrintStr( vStr, "(" );
556 Bac_ManWriteConcat( p, iTerm, Range );
557 Vec_StrPrintStr( vStr, ")" );
558 iSig++;
559 }
560 Bac_BoxForEachBoMain( p, iObj, iTerm, k )
561 {
562 Range = Vec_IntEntry( vBits, iSig );
563 Vec_StrPrintStr( vStr, iSig ? ", " : "" );
564 if ( Vec_StrSize(vStr) > StartPos + 70 )
565 {
566 StartPos = Vec_StrSize(vStr);
567 Vec_StrPrintStr( vStr, "\n " );
568 }
569 Vec_StrPrintStr( vStr, "." );
570 Vec_StrPush( vStr, pSymbs[iSig] );
571 Vec_StrPrintStr( vStr, "(" );
572 Bac_ManWriteConcat( p, iTerm, Range );
573 Vec_StrPrintStr( vStr, ")" );
574 iSig++;
575 }
576 assert( iSig == Vec_IntSize(vBits) );
577 }
578 Vec_StrPrintStr( vStr, ");\n" );
579 }
580}
581void Bac_ManWriteVerilogNtk( Bac_Ntk_t * p, int fUseAssign )
582{
583 char * pKeyword[4] = { "wire ", "input ", "output ", "inout " };
584 Vec_Str_t * vStr = p->pDesign->vOut;
585 int k, iObj, iTerm, Value, Beg, End, Length, fHaveWires, StartPos;
586// assert( Bac_NtkInfoNum(p) );
587 assert( Vec_IntSize(&p->vFanin) == Bac_NtkObjNum(p) );
588// Bac_NtkPrint( p );
589 // write header
590 Vec_StrPrintStr( vStr, "module " );
591 Vec_StrPrintStr( vStr, Bac_NtkName(p) );
592 Vec_StrPrintStr( vStr, " (\n " );
593 StartPos = Vec_StrSize(vStr);
594 Vec_IntForEachEntryTriple( &p->vInfo, Value, Beg, End, k )
595 if ( Abc_Lit2Att2(Value) != 0 )
596 {
597 Vec_StrPrintStr( vStr, k ? ", " : "" );
598 if ( Vec_StrSize(vStr) > StartPos + 70 )
599 {
600 StartPos = Vec_StrSize(vStr);
601 Vec_StrPrintStr( vStr, "\n " );
602 }
603 Bac_ManWriteVar( p, Abc_Lit2Var2(Value) );
604 }
605 Vec_StrPrintStr( vStr, "\n );\n" );
606 // write inputs/outputs
607 Vec_IntForEachEntryTriple( &p->vInfo, Value, Beg, End, k )
608 if ( Abc_Lit2Att2(Value) != 0 )
609 {
610 Vec_StrPrintStr( vStr, " " );
611 Vec_StrPrintStr( vStr, pKeyword[Abc_Lit2Att2(Value)] );
612 if ( Beg >= 0 )
613 Bac_ManWriteRange( p, Beg, End );
614 Bac_ManWriteVar( p, Abc_Lit2Var2(Value) );
615 Vec_StrPrintStr( vStr, ";\n" );
616 }
617 Vec_StrPrintStr( vStr, "\n" );
618 // write word-level wires
619 Bac_NtkForEachBox( p, iObj )
620 if ( !Bac_ObjIsConst(p, iObj) )
621 Bac_BoxForEachBo( p, iObj, iTerm, k )
622 if ( Bac_ObjNameType(p, iTerm) == BAC_NAME_WORD || Bac_ObjNameType(p, iTerm) == BAC_NAME_INFO )
623 {
624 Vec_StrPrintStr( vStr, " wire " );
625 Bac_ManWriteRange( p, Bac_ManFindRealIndex(p, iTerm), Bac_ManFindRealIndex(p, iTerm + Bac_ObjGetRange(p, iTerm) - 1) );
626 Bac_ManWriteVar( p, Bac_ManFindRealNameId(p, iTerm) );
627 Vec_StrPrintStr( vStr, ";\n" );
628 }
629 // check if there are any wires left
630 fHaveWires = 0;
631 Bac_NtkForEachBox( p, iObj )
632 if ( !Bac_ObjIsConst(p, iObj) )
633 Bac_BoxForEachBo( p, iObj, iTerm, k )
634 if ( Bac_ObjNameType(p, iTerm) == BAC_NAME_BIN )
635 { fHaveWires = 1; iObj = Bac_NtkObjNum(p); break; }
636 // write bit-level wires
637 if ( fHaveWires )
638 {
639 Length = 7;
640 Vec_StrPrintStr( vStr, "\n wire " );
641 Bac_NtkForEachBox( p, iObj )
642 if ( !Bac_ObjIsConst(p, iObj) )
643 Bac_BoxForEachBo( p, iObj, iTerm, k )
644 if ( Bac_ObjNameType(p, iTerm) == BAC_NAME_BIN )
645 {
646 if ( Length > 72 )
647 Vec_StrPrintStr( vStr, ";\n wire " ), Length = 7;
648 if ( Length > 7 )
649 Vec_StrPrintStr( vStr, ", " );
650 Vec_StrPrintStr( vStr, Bac_ObjNameStr(p, iTerm) );
651 Length += strlen(Bac_ObjNameStr(p, iTerm));
652 }
653 Vec_StrPrintStr( vStr, ";\n" );
654 }
655 Vec_StrPrintStr( vStr, "\n" );
656 // write objects
657 Bac_ManWriteVerilogBoxes( p, fUseAssign );
658 Vec_StrPrintStr( vStr, "endmodule\n\n" );
659}
660void Bac_ManWriteVerilog( char * pFileName, Bac_Man_t * p, int fUseAssign )
661{
662 Bac_Ntk_t * pNtk; int i;
663 // check the library
664 if ( p->pMioLib && p->pMioLib != Abc_FrameReadLibGen() )
665 {
666 printf( "Genlib library used in the mapped design is not longer a current library.\n" );
667 return;
668 }
669 // derive the stream
670 p->vOut = Vec_StrAlloc( 10000 );
671 p->vOut2 = Vec_StrAlloc( 1000 );
672 Vec_StrPrintStr( p->vOut, "// Design \"" );
673 Vec_StrPrintStr( p->vOut, Bac_ManName(p) );
674 Vec_StrPrintStr( p->vOut, "\" written via CBA package in ABC on " );
675 Vec_StrPrintStr( p->vOut, Extra_TimeStamp() );
676 Vec_StrPrintStr( p->vOut, "\n\n" );
678 Bac_ManForEachNtk( p, pNtk, i )
679 Bac_ManWriteVerilogNtk( pNtk, fUseAssign );
680 // dump into file
681 if ( p->vOut && Vec_StrSize(p->vOut) > 0 )
682 {
683 FILE * pFile = fopen( pFileName, "wb" );
684 if ( pFile == NULL )
685 printf( "Cannot open file \"%s\" for writing.\n", pFileName );
686 else
687 {
688 fwrite( Vec_StrArray(p->vOut), 1, Vec_StrSize(p->vOut), pFile );
689 fclose( pFile );
690 }
691 }
692 Vec_StrFreeP( &p->vOut );
693 Vec_StrFreeP( &p->vOut2 );
694}
695
696
700
701
703
#define ABC_NAMESPACE_IMPL_START
#define ABC_NAMESPACE_IMPL_END
struct Psr_Ntk_t_ Psr_Ntk_t
BASIC TYPES ///.
Definition bacPrs.h:51
Psr_ManType_t
INCLUDES ///.
Definition bacPrs.h:39
@ BAC_PRS_CONST
Definition bacPrs.h:42
@ BAC_PRS_CONCAT
Definition bacPrs.h:43
@ BAC_PRS_NAME
Definition bacPrs.h:40
@ BAC_PRS_SLICE
Definition bacPrs.h:41
#define Psr_NtkForEachBox(p, vVec, i)
Definition bacPrs.h:147
void Psr_ManWriteVerilog(char *pFileName, Vec_Ptr_t *vPrs)
void Bac_ManWriteVerilogBoxes(Bac_Ntk_t *p, int fUseAssign)
void Psr_ManWriteVerilogArray(FILE *pFile, Psr_Ntk_t *p, Vec_Int_t *vSigs, int Start, int Stop, int fOdd)
Definition bacWriteVer.c:67
void Bac_ManWriteVerilogNtk(Bac_Ntk_t *p, int fUseAssign)
void Bac_ManWriteVerilog(char *pFileName, Bac_Man_t *p, int fUseAssign)
struct Bac_Man_t_ Bac_Man_t
Definition bac.h:142
struct Bac_Ntk_t_ Bac_Ntk_t
Definition bac.h:141
#define Bac_BoxForEachBo(p, iBox, iTerm, i)
Definition bac.h:377
char * Bac_NtkGenerateName(Bac_Ntk_t *p, Bac_ObjType_t Type, Vec_Int_t *vBits)
Definition bacNtk.c:142
#define Bac_BoxForEachBoMain(p, iBox, iTerm, i)
Definition bac.h:384
void Bac_ManAssignInternWordNames(Bac_Man_t *p)
Definition bacNtk.c:392
#define Bac_BoxForEachBi(p, iBox, iTerm, i)
Definition bac.h:375
@ BAC_NAME_WORD
Definition bac.h:135
@ BAC_NAME_INFO
Definition bac.h:136
@ BAC_NAME_INDEX
Definition bac.h:137
@ BAC_NAME_BIN
Definition bac.h:134
#define Bac_ManForEachNtk(p, pNtk, i)
MACRO DEFINITIONS ///.
Definition bac.h:334
#define Bac_NtkForEachBox(p, i)
Definition bac.h:354
#define Bac_BoxForEachBiMain(p, iBox, iTerm, i)
Definition bac.h:382
Bac_ObjType_t
INCLUDES ///.
Definition bac.h:43
@ BAC_BOX_SHARP
Definition bac.h:63
@ BAC_BOX_XNOR
Definition bac.h:62
@ BAC_BOX_AND
Definition bac.h:57
@ BAC_BOX_INV
Definition bac.h:56
@ BAC_BOX_CT
Definition bac.h:52
@ BAC_BOX_CX
Definition bac.h:53
@ BAC_BOX_BUF
Definition bac.h:55
@ BAC_BOX_CF
Definition bac.h:51
@ BAC_BOX_XOR
Definition bac.h:61
@ BAC_BOX_MUX
Definition bac.h:65
@ BAC_BOX_OR
Definition bac.h:59
@ BAC_BOX_NAND
Definition bac.h:58
@ BAC_BOX_SHARPL
Definition bac.h:64
@ BAC_BOX_CZ
Definition bac.h:54
@ BAC_BOX_NOR
Definition bac.h:60
ABC_DLL void * Abc_FrameReadLibGen()
Definition mainFrame.c:59
typedefABC_NAMESPACE_IMPL_START struct Vec_Int_t_ Vec_Int_t
DECLARATIONS ///.
Definition bblif.c:37
struct Vec_Str_t_ Vec_Str_t
Definition bblif.c:46
Cube * p
Definition exorList.c:222
char * Extra_TimeStamp()
struct Mio_LibraryStruct_t_ Mio_Library_t
Definition mio.h:42
Mio_Gate_t * Mio_LibraryReadGateByName(Mio_Library_t *pLib, char *pName, char *pOutName)
Definition mioApi.c:105
char * Mio_GateReadPinName(Mio_Gate_t *pGate, int iPin)
Definition mioApi.c:230
char * Mio_GateReadOutName(Mio_Gate_t *pGate)
Definition mioApi.c:170
struct Mio_GateStruct_t_ Mio_Gate_t
Definition mio.h:43
Vec_Int_t vInfo
Definition bac.h:157
int iModuleName
Definition bacPrs.h:55
char * Abc_NamStr(Abc_Nam_t *p, int NameId)
Definition utilNam.c:555
#define assert(ex)
Definition util_old.h:213
int strlen()
#define Vec_IntForEachEntryDouble(vVec, Entry1, Entry2, i)
Definition vecInt.h:72
#define Vec_IntForEachEntry(vVec, Entry, i)
MACRO DEFINITIONS ///.
Definition vecInt.h:54
#define Vec_IntForEachEntryTwo(vVec1, vVec2, Entry1, Entry2, i)
Definition vecInt.h:66
#define Vec_IntForEachEntryStartStop(vVec, Entry, i, Start, Stop)
Definition vecInt.h:60
#define Vec_IntForEachEntryTriple(vVec, Entry1, Entry2, Entry3, i)
Definition vecInt.h:76
typedefABC_NAMESPACE_HEADER_START struct Vec_Ptr_t_ Vec_Ptr_t
INCLUDES ///.
Definition vecPtr.h:42
#define Vec_PtrForEachEntry(Type, vVec, pEntry, i)
MACRO DEFINITIONS ///.
Definition vecPtr.h:55