ABC: A System for Sequential Synthesis and Verification
 
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bacWriteVer.c File Reference
#include "bac.h"
#include "bacPrs.h"
#include "map/mio/mio.h"
#include "base/main/main.h"
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Functions

void Psr_ManWriteVerilogArray (FILE *pFile, Psr_Ntk_t *p, Vec_Int_t *vSigs, int Start, int Stop, int fOdd)
 
void Psr_ManWriteVerilog (char *pFileName, Vec_Ptr_t *vPrs)
 
void Bac_ManWriteVerilogBoxes (Bac_Ntk_t *p, int fUseAssign)
 
void Bac_ManWriteVerilogNtk (Bac_Ntk_t *p, int fUseAssign)
 
void Bac_ManWriteVerilog (char *pFileName, Bac_Man_t *p, int fUseAssign)
 

Function Documentation

◆ Bac_ManWriteVerilog()

void Bac_ManWriteVerilog ( char * pFileName,
Bac_Man_t * p,
int fUseAssign )

Definition at line 660 of file bacWriteVer.c.

661{
662 Bac_Ntk_t * pNtk; int i;
663 // check the library
664 if ( p->pMioLib && p->pMioLib != Abc_FrameReadLibGen() )
665 {
666 printf( "Genlib library used in the mapped design is not longer a current library.\n" );
667 return;
668 }
669 // derive the stream
670 p->vOut = Vec_StrAlloc( 10000 );
671 p->vOut2 = Vec_StrAlloc( 1000 );
672 Vec_StrPrintStr( p->vOut, "// Design \"" );
673 Vec_StrPrintStr( p->vOut, Bac_ManName(p) );
674 Vec_StrPrintStr( p->vOut, "\" written via CBA package in ABC on " );
675 Vec_StrPrintStr( p->vOut, Extra_TimeStamp() );
676 Vec_StrPrintStr( p->vOut, "\n\n" );
677 Bac_ManAssignInternWordNames( p );
678 Bac_ManForEachNtk( p, pNtk, i )
679 Bac_ManWriteVerilogNtk( pNtk, fUseAssign );
680 // dump into file
681 if ( p->vOut && Vec_StrSize(p->vOut) > 0 )
682 {
683 FILE * pFile = fopen( pFileName, "wb" );
684 if ( pFile == NULL )
685 printf( "Cannot open file \"%s\" for writing.\n", pFileName );
686 else
687 {
688 fwrite( Vec_StrArray(p->vOut), 1, Vec_StrSize(p->vOut), pFile );
689 fclose( pFile );
690 }
691 }
692 Vec_StrFreeP( &p->vOut );
693 Vec_StrFreeP( &p->vOut2 );
694}
Bac_ManWriteVerilogNtk
void Bac_ManWriteVerilogNtk(Bac_Ntk_t *p, int fUseAssign)
Definition bacWriteVer.c:581
Bac_Ntk_t
struct Bac_Ntk_t_ Bac_Ntk_t
Definition bac.h:141
Bac_ManAssignInternWordNames
void Bac_ManAssignInternWordNames(Bac_Man_t *p)
Definition bacNtk.c:392
Bac_ManForEachNtk
#define Bac_ManForEachNtk(p, pNtk, i)
MACRO DEFINITIONS ///.
Definition bac.h:334
Abc_FrameReadLibGen
ABC_DLL void * Abc_FrameReadLibGen()
Definition mainFrame.c:59
p
Cube * p
Definition exorList.c:222
Extra_TimeStamp
char * Extra_TimeStamp()
Definition extraUtilFile.c:465
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◆ Bac_ManWriteVerilogBoxes()

void Bac_ManWriteVerilogBoxes ( Bac_Ntk_t * p,
int fUseAssign )

Definition at line 472 of file bacWriteVer.c.

473{
474 Vec_Str_t * vStr = p->pDesign->vOut;
475 int iObj, k, i, o, StartPos;
476 Bac_NtkForEachBox( p, iObj ) // .subckt/.gate/box (formal/actual binding)
477 {
478 // skip constants
479 if ( Bac_ObjIsConst(p, iObj) )
480 continue;
481 // write mapped
482 if ( Bac_ObjIsGate(p, iObj) )
483 {
484 Bac_ManWriteGate( p, iObj );
485 continue;
486 }
487 // write primitives as assign-statements
488 if ( !Bac_ObjIsBoxUser(p, iObj) && fUseAssign )
489 {
490 Bac_ManWriteAssign( p, iObj );
491 continue;
492 }
493 // write header
494 StartPos = Vec_StrSize(vStr);
495 if ( Bac_ObjIsBoxUser(p, iObj) )
496 {
497 int Value, Beg, End, Range;
498 Bac_Ntk_t * pModel = Bac_BoxNtk( p, iObj );
499 Vec_StrPrintStr( vStr, " " );
500 Vec_StrPrintStr( vStr, Bac_NtkName(pModel) );
501 Vec_StrPrintStr( vStr, " " );
502 Vec_StrPrintStr( vStr, Bac_ObjName(p, iObj) ? Bac_ObjNameStr(p, iObj) : "" );
503 Vec_StrPrintStr( vStr, " (" );
504 // write arguments
505 i = o = 0;
506 assert( Bac_NtkInfoNum(pModel) );
507 Vec_IntForEachEntryTriple( &pModel->vInfo, Value, Beg, End, k )
508 {
509 int NameId = Abc_Lit2Var2( Value );
510 int Type = Abc_Lit2Att2( Value );
511 Vec_StrPrintStr( vStr, k ? ", " : "" );
512 if ( Vec_StrSize(vStr) > StartPos + 70 )
513 {
514 StartPos = Vec_StrSize(vStr);
515 Vec_StrPrintStr( vStr, "\n " );
516 }
517 Vec_StrPrintStr( vStr, "." );
518 Vec_StrPrintStr( vStr, Bac_NtkStr(p, NameId) );
519 Vec_StrPrintStr( vStr, "(" );
520 Range = Bac_InfoRange( Beg, End );
521 assert( Range > 0 );
522 if ( Type == 1 )
523 Bac_ManWriteConcat( p, Bac_BoxBi(p, iObj, i), Range ), i += Range;
524 else if ( Type == 2 )
525 Bac_ManWriteConcat( p, Bac_BoxBo(p, iObj, o), Range ), o += Range;
526 else assert( 0 );
527 Vec_StrPrintStr( vStr, ")" );
528 }
529 assert( i == Bac_BoxBiNum(p, iObj) );
530 assert( o == Bac_BoxBoNum(p, iObj) );
531 }
532 else
533 {
534 int iTerm, k, Range, iSig = 0;
535 Vec_Int_t * vBits = Bac_BoxCollectRanges( p, iObj );
536 char * pName = Bac_NtkGenerateName( p, Bac_ObjType(p, iObj), vBits );
537 char * pSymbs = Bac_ManPrimSymb( p->pDesign, Bac_ObjType(p, iObj) );
538 Vec_StrPrintStr( vStr, " " );
539 Vec_StrPrintStr( vStr, pName );
540 Vec_StrPrintStr( vStr, " " );
541 Vec_StrPrintStr( vStr, Bac_ObjName(p, iObj) ? Bac_ObjNameStr(p, iObj) : "" );
542 Vec_StrPrintStr( vStr, " (" );
543 // write inputs
544 Bac_BoxForEachBiMain( p, iObj, iTerm, k )
545 {
546 Range = Vec_IntEntry( vBits, iSig );
547 Vec_StrPrintStr( vStr, iSig ? ", " : "" );
548 if ( Vec_StrSize(vStr) > StartPos + 70 )
549 {
550 StartPos = Vec_StrSize(vStr);
551 Vec_StrPrintStr( vStr, "\n " );
552 }
553 Vec_StrPrintStr( vStr, "." );
554 Vec_StrPush( vStr, pSymbs[iSig] );
555 Vec_StrPrintStr( vStr, "(" );
556 Bac_ManWriteConcat( p, iTerm, Range );
557 Vec_StrPrintStr( vStr, ")" );
558 iSig++;
559 }
560 Bac_BoxForEachBoMain( p, iObj, iTerm, k )
561 {
562 Range = Vec_IntEntry( vBits, iSig );
563 Vec_StrPrintStr( vStr, iSig ? ", " : "" );
564 if ( Vec_StrSize(vStr) > StartPos + 70 )
565 {
566 StartPos = Vec_StrSize(vStr);
567 Vec_StrPrintStr( vStr, "\n " );
568 }
569 Vec_StrPrintStr( vStr, "." );
570 Vec_StrPush( vStr, pSymbs[iSig] );
571 Vec_StrPrintStr( vStr, "(" );
572 Bac_ManWriteConcat( p, iTerm, Range );
573 Vec_StrPrintStr( vStr, ")" );
574 iSig++;
575 }
576 assert( iSig == Vec_IntSize(vBits) );
577 }
578 Vec_StrPrintStr( vStr, ");\n" );
579 }
580}
Bac_NtkGenerateName
char * Bac_NtkGenerateName(Bac_Ntk_t *p, Bac_ObjType_t Type, Vec_Int_t *vBits)
Definition bacNtk.c:142
Bac_BoxForEachBoMain
#define Bac_BoxForEachBoMain(p, iBox, iTerm, i)
Definition bac.h:384
Bac_NtkForEachBox
#define Bac_NtkForEachBox(p, i)
Definition bac.h:354
Bac_BoxForEachBiMain
#define Bac_BoxForEachBiMain(p, iBox, iTerm, i)
Definition bac.h:382
Vec_Int_t
typedefABC_NAMESPACE_IMPL_START struct Vec_Int_t_ Vec_Int_t
DECLARATIONS ///.
Definition bblif.c:37
Vec_Str_t
struct Vec_Str_t_ Vec_Str_t
Definition bblif.c:46
Bac_Ntk_t_::vInfo
Vec_Int_t vInfo
Definition bac.h:157
assert
#define assert(ex)
Definition util_old.h:213
Vec_IntForEachEntryTriple
#define Vec_IntForEachEntryTriple(vVec, Entry1, Entry2, Entry3, i)
Definition vecInt.h:76
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◆ Bac_ManWriteVerilogNtk()

void Bac_ManWriteVerilogNtk ( Bac_Ntk_t * p,
int fUseAssign )

Definition at line 581 of file bacWriteVer.c.

582{
583 char * pKeyword[4] = { "wire ", "input ", "output ", "inout " };
584 Vec_Str_t * vStr = p->pDesign->vOut;
585 int k, iObj, iTerm, Value, Beg, End, Length, fHaveWires, StartPos;
586// assert( Bac_NtkInfoNum(p) );
587 assert( Vec_IntSize(&p->vFanin) == Bac_NtkObjNum(p) );
588// Bac_NtkPrint( p );
589 // write header
590 Vec_StrPrintStr( vStr, "module " );
591 Vec_StrPrintStr( vStr, Bac_NtkName(p) );
592 Vec_StrPrintStr( vStr, " (\n " );
593 StartPos = Vec_StrSize(vStr);
594 Vec_IntForEachEntryTriple( &p->vInfo, Value, Beg, End, k )
595 if ( Abc_Lit2Att2(Value) != 0 )
596 {
597 Vec_StrPrintStr( vStr, k ? ", " : "" );
598 if ( Vec_StrSize(vStr) > StartPos + 70 )
599 {
600 StartPos = Vec_StrSize(vStr);
601 Vec_StrPrintStr( vStr, "\n " );
602 }
603 Bac_ManWriteVar( p, Abc_Lit2Var2(Value) );
604 }
605 Vec_StrPrintStr( vStr, "\n );\n" );
606 // write inputs/outputs
607 Vec_IntForEachEntryTriple( &p->vInfo, Value, Beg, End, k )
608 if ( Abc_Lit2Att2(Value) != 0 )
609 {
610 Vec_StrPrintStr( vStr, " " );
611 Vec_StrPrintStr( vStr, pKeyword[Abc_Lit2Att2(Value)] );
612 if ( Beg >= 0 )
613 Bac_ManWriteRange( p, Beg, End );
614 Bac_ManWriteVar( p, Abc_Lit2Var2(Value) );
615 Vec_StrPrintStr( vStr, ";\n" );
616 }
617 Vec_StrPrintStr( vStr, "\n" );
618 // write word-level wires
619 Bac_NtkForEachBox( p, iObj )
620 if ( !Bac_ObjIsConst(p, iObj) )
621 Bac_BoxForEachBo( p, iObj, iTerm, k )
622 if ( Bac_ObjNameType(p, iTerm) == BAC_NAME_WORD || Bac_ObjNameType(p, iTerm) == BAC_NAME_INFO )
623 {
624 Vec_StrPrintStr( vStr, " wire " );
625 Bac_ManWriteRange( p, Bac_ManFindRealIndex(p, iTerm), Bac_ManFindRealIndex(p, iTerm + Bac_ObjGetRange(p, iTerm) - 1) );
626 Bac_ManWriteVar( p, Bac_ManFindRealNameId(p, iTerm) );
627 Vec_StrPrintStr( vStr, ";\n" );
628 }
629 // check if there are any wires left
630 fHaveWires = 0;
631 Bac_NtkForEachBox( p, iObj )
632 if ( !Bac_ObjIsConst(p, iObj) )
633 Bac_BoxForEachBo( p, iObj, iTerm, k )
634 if ( Bac_ObjNameType(p, iTerm) == BAC_NAME_BIN )
635 { fHaveWires = 1; iObj = Bac_NtkObjNum(p); break; }
636 // write bit-level wires
637 if ( fHaveWires )
638 {
639 Length = 7;
640 Vec_StrPrintStr( vStr, "\n wire " );
641 Bac_NtkForEachBox( p, iObj )
642 if ( !Bac_ObjIsConst(p, iObj) )
643 Bac_BoxForEachBo( p, iObj, iTerm, k )
644 if ( Bac_ObjNameType(p, iTerm) == BAC_NAME_BIN )
645 {
646 if ( Length > 72 )
647 Vec_StrPrintStr( vStr, ";\n wire " ), Length = 7;
648 if ( Length > 7 )
649 Vec_StrPrintStr( vStr, ", " );
650 Vec_StrPrintStr( vStr, Bac_ObjNameStr(p, iTerm) );
651 Length += strlen(Bac_ObjNameStr(p, iTerm));
652 }
653 Vec_StrPrintStr( vStr, ";\n" );
654 }
655 Vec_StrPrintStr( vStr, "\n" );
656 // write objects
657 Bac_ManWriteVerilogBoxes( p, fUseAssign );
658 Vec_StrPrintStr( vStr, "endmodule\n\n" );
659}
Bac_ManWriteVerilogBoxes
void Bac_ManWriteVerilogBoxes(Bac_Ntk_t *p, int fUseAssign)
Definition bacWriteVer.c:472
Bac_BoxForEachBo
#define Bac_BoxForEachBo(p, iBox, iTerm, i)
Definition bac.h:377
BAC_NAME_WORD
@ BAC_NAME_WORD
Definition bac.h:135
BAC_NAME_INFO
@ BAC_NAME_INFO
Definition bac.h:136
BAC_NAME_BIN
@ BAC_NAME_BIN
Definition bac.h:134
strlen
int strlen()
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◆ Psr_ManWriteVerilog()

void Psr_ManWriteVerilog ( char * pFileName,
Vec_Ptr_t * vPrs )

Definition at line 166 of file bacWriteVer.c.

167{
168 Psr_Ntk_t * pNtk = Psr_ManRoot(vPrs); int i;
169 FILE * pFile = fopen( pFileName, "wb" );
170 if ( pFile == NULL )
171 {
172 printf( "Cannot open output file \"%s\".\n", pFileName );
173 return;
174 }
175 fprintf( pFile, "// Design \"%s\" written by ABC on %s\n\n", Psr_NtkStr(pNtk, pNtk->iModuleName), Extra_TimeStamp() );
176 Vec_PtrForEachEntry( Psr_Ntk_t *, vPrs, pNtk, i )
177 Psr_ManWriteVerilogNtk( pFile, pNtk );
178 fclose( pFile );
179}
Psr_Ntk_t
struct Psr_Ntk_t_ Psr_Ntk_t
BASIC TYPES ///.
Definition bacPrs.h:51
Psr_Ntk_t_::iModuleName
int iModuleName
Definition bacPrs.h:55
Vec_PtrForEachEntry
#define Vec_PtrForEachEntry(Type, vVec, pEntry, i)
MACRO DEFINITIONS ///.
Definition vecPtr.h:55
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◆ Psr_ManWriteVerilogArray()

void Psr_ManWriteVerilogArray ( FILE * pFile,
Psr_Ntk_t * p,
Vec_Int_t * vSigs,
int Start,
int Stop,
int fOdd )

Definition at line 67 of file bacWriteVer.c.

68{
69 int i, Sig;
70 assert( Vec_IntSize(vSigs) > 0 );
71 Vec_IntForEachEntryStartStop( vSigs, Sig, i, Start, Stop )
72 {
73 if ( fOdd && !(i & 1) )
74 continue;
75 Psr_ManWriteVerilogSignal( pFile, p, Sig );
76 fprintf( pFile, "%s", i == Stop - 1 ? "" : ", " );
77 }
78}
Vec_IntForEachEntryStartStop
#define Vec_IntForEachEntryStartStop(vVec, Entry, i, Start, Stop)
Definition vecInt.h:60