ABC: A System for Sequential Synthesis and Verification
 
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cecSim.c
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1
20
21#include "cecInt.h"
22#include "aig/gia/giaAig.h"
23#include "misc/util/utilTruth.h"
24
25
27
31
32#define SIM_RANDS 113
33
34typedef struct Cec_ManS_t_ Cec_ManS_t;
53
54static inline word * Cec_ManSSim( Cec_ManS_t * p, int iNode, int Value ) { return Vec_WrdEntryP(p->vSims, p->nWords*(iNode+iNode+Value)); }
55
59
72{
73 Cec_ManS_t * p; int i;
74 p = ABC_ALLOC( Cec_ManS_t, 1 );
75 memset( p, 0, sizeof(Cec_ManS_t) );
76 p->nWords = nWords;
77 p->pAig = pAig;
78 p->vInputs = Vec_IntAlloc( 100 );
79 p->vLevels = Vec_WecStart( Gia_ManLevelNum(pAig) + 1 );
80 p->vSims = Vec_WrdStart( Gia_ManObjNum(pAig) * nWords * 2 );
81 p->pTemp[0] = ABC_ALLOC( word, 4*nWords );
82 for ( i = 1; i < 4; i++ )
83 p->pTemp[i] = p->pTemp[i-1] + nWords;
84 for ( i = 0; i < SIM_RANDS; i++ )
85 p->Rands[i] = Gia_ManRandomW(0);
86 return p;
87}
89{
90 Vec_IntFree( p->vInputs );
91 Vec_WecFree( p->vLevels );
92 Vec_WrdFree( p->vSims );
93 ABC_FREE( p->pTemp[0] );
94 ABC_FREE( p );
95}
96
109{
110 int Value0, Value1;
111 Gia_Obj_t * pObj = Gia_ManObj( p, iObj );
112 if ( iObj == 0 ) return 0;
113 if ( Gia_ObjIsTravIdCurrentId(p, iObj) )
114 return pObj->fMark1;
115 Gia_ObjSetTravIdCurrentId(p, iObj);
116 if ( Gia_ObjIsCi(pObj) )
117 return pObj->fMark1;
118 assert( Gia_ObjIsAnd(pObj) );
119 Value0 = Cec_ManSVerify_rec( p, Gia_ObjFaninId0(pObj, iObj) ) ^ Gia_ObjFaninC0(pObj);
120 Value1 = Cec_ManSVerify_rec( p, Gia_ObjFaninId1(pObj, iObj) ) ^ Gia_ObjFaninC1(pObj);
121 return pObj->fMark1 = Gia_ObjIsXor(pObj) ? Value0 ^ Value1 : Value0 & Value1;
122}
123void Cec_ManSVerifyTwo( Gia_Man_t * p, int iObj0, int iObj1 )
124{
125 int Value0, Value1;
127 Value0 = Cec_ManSVerify_rec( p, iObj0 );
128 Value1 = Cec_ManSVerify_rec( p, iObj1 );
129 if ( (Value0 ^ Value1) == Gia_ObjPhaseDiff(p, iObj0, iObj1) )
130 printf( "CEX verification FAILED for obj %d and obj %d.\n", iObj0, iObj1 );
131// else
132// printf( "CEX verification succeeded for obj %d and obj %d.\n", iObj0, iObj1 );;
133}
134void Cec_ManSVerify( Cec_ManS_t * p, int iObj0, int iObj1 )
135{
136 int fDoVerify = 0;
137 int w, i, iObj, nCares;
138 word * pCare = Vec_WrdArray(p->vSims);
139 if ( Vec_IntSize(p->vInputs) == 0 )
140 {
141 printf( "No primary inputs.\n" );
142 return;
143 }
144 Vec_IntForEachEntry( p->vInputs, iObj, i )
145 {
146 word * pSim_0 = Cec_ManSSim( p, iObj, 0 );
147 word * pSim_1 = Cec_ManSSim( p, iObj, 1 );
148 if ( p->nWords == 1 )
149 pCare[0] |= pSim_0[0] & pSim_1[0];
150 else
151 Abc_TtOrAnd( pCare, pSim_0, pSim_1, p->nWords );
152 }
153 nCares = Abc_TtCountOnesVec( pCare, p->nWords );
154 if ( nCares == 64*p->nWords )
155 {
156 printf( "No CEXes.\n" );
157 return;
158 }
159 assert( Vec_IntSize(p->vInputs) > 0 );
160 for ( w = 0; w < 64*p->nWords; w++ )
161 {
162 if ( Abc_TtGetBit(pCare, w) )
163 continue;
164 if ( !fDoVerify )
165 continue;
166 Vec_IntForEachEntry( p->vInputs, iObj, i )
167 Gia_ManObj(p->pAig, iObj)->fMark1 = Abc_TtGetBit( Cec_ManSSim(p, iObj, 1), w );
168 Cec_ManSVerifyTwo( p->pAig, iObj0, iObj1 );
169 }
170 printf( "Considered %d CEXes of nodes %d and %d.\n", 64*p->nWords - nCares, iObj0, iObj1 );
171}
172
184void Cec_ManSRunImply( Cec_ManS_t * p, int iNode )
185{
186 Gia_Obj_t * pNode = Gia_ManObj( p->pAig, iNode );
187 if ( Gia_ObjIsAnd(pNode) )
188 {
189 int iFan0 = Gia_ObjFaninId0( pNode, iNode );
190 int iFan1 = Gia_ObjFaninId1( pNode, iNode );
191 word * pSim__ = Cec_ManSSim( p, 0, 0 );
192 word * pSim_0 = Cec_ManSSim( p, iNode, 0 );
193 word * pSim_1 = Cec_ManSSim( p, iNode, 1 );
194 word * pSim00 = Cec_ManSSim( p, iFan0, Gia_ObjFaninC0(pNode) );
195 word * pSim01 = Cec_ManSSim( p, iFan0, !Gia_ObjFaninC0(pNode) );
196 word * pSim10 = Cec_ManSSim( p, iFan1, Gia_ObjFaninC1(pNode) );
197 word * pSim11 = Cec_ManSSim( p, iFan1, !Gia_ObjFaninC1(pNode) );
198 if ( p->nWords == 1 )
199 {
200 pSim_0[0] |= pSim00[0] | pSim10[0];
201 pSim_1[0] |= pSim01[0] & pSim11[0];
202 pSim__[0] |= pSim_0[0] & pSim_1[0];
203 pSim_0[0] &= ~pSim__[0];
204 pSim_1[0] &= ~pSim__[0];
205 }
206 else
207 {
208 Abc_TtOr( pSim_0, pSim_0, pSim00, p->nWords );
209 Abc_TtOr( pSim_0, pSim_0, pSim10, p->nWords );
210 Abc_TtOrAnd( pSim_1, pSim01, pSim11, p->nWords );
211 Abc_TtOrAnd( pSim__, pSim_0, pSim_1, p->nWords );
212 Abc_TtAndSharp( pSim_0, pSim_0, pSim__, p->nWords, 1 );
213 Abc_TtAndSharp( pSim_1, pSim_1, pSim__, p->nWords, 1 );
214 }
215 }
216}
218{
219 Gia_Obj_t * pNode = Gia_ManObj( p->pAig, iNode );
220 int iFan0 = Gia_ObjFaninId0( pNode, iNode );
221 int iFan1 = Gia_ObjFaninId1( pNode, iNode );
222 word * pSim_0 = Cec_ManSSim( p, iNode, 0 );
223 word * pSim_1 = Cec_ManSSim( p, iNode, 1 );
224 if ( Abc_TtIsConst0(pSim_0, p->nWords) && Abc_TtIsConst0(pSim_1, p->nWords) )
225 {
226 p->nSkipped++;
227 return 0;
228 }
229 p->nVisited++;
230 //Cec_ManSRunImply( p, iFan0 );
231 //Cec_ManSRunImply( p, iFan1 );
232 {
233 word * pSim__ = Cec_ManSSim( p, 0, 0 );
234 word * pSim00 = Cec_ManSSim( p, iFan0, Gia_ObjFaninC0(pNode) );
235 word * pSim01 = Cec_ManSSim( p, iFan0, !Gia_ObjFaninC0(pNode) );
236 word * pSim10 = Cec_ManSSim( p, iFan1, Gia_ObjFaninC1(pNode) );
237 word * pSim11 = Cec_ManSSim( p, iFan1, !Gia_ObjFaninC1(pNode) );
238 p->iRand = p->iRand == SIM_RANDS-1 ? 0 : p->iRand + 1;
239 if ( p->nWords == 1 )
240 {
241 pSim01[0] |= pSim_1[0];
242 pSim11[0] |= pSim_1[0];
243
244 pSim00[0] |= pSim_0[0] & (pSim11[0] | ~p->Rands[p->iRand]);
245 pSim10[0] |= pSim_0[0] & (pSim01[0] | p->Rands[p->iRand]);
246
247 pSim__[0] |= pSim00[0] & pSim01[0];
248 pSim__[0] |= pSim10[0] & pSim11[0];
249
250 pSim00[0] &= ~pSim__[0];
251 pSim01[0] &= ~pSim__[0];
252 pSim10[0] &= ~pSim__[0];
253 pSim11[0] &= ~pSim__[0];
254 }
255 else
256 {
257 int w;
258 for ( w = 0; w < p->nWords; w++ )
259 p->pTemp[0][w] = ~p->Rands[(p->iRand + w) % SIM_RANDS];
260
261 Abc_TtOr( pSim01, pSim01, pSim_1, p->nWords );
262 Abc_TtOr( pSim11, pSim11, pSim_1, p->nWords );
263
264 Abc_TtOr( p->pTemp[1], pSim11, p->pTemp[0], p->nWords );
265 Abc_TtOrAnd( pSim00, pSim_0, p->pTemp[1], p->nWords );
266
267 Abc_TtNot( p->pTemp[0], p->nWords );
268 Abc_TtOr( p->pTemp[1], pSim01, p->pTemp[0], p->nWords );
269 Abc_TtOrAnd( pSim10, pSim_0, p->pTemp[1], p->nWords );
270
271 Abc_TtOrAnd( pSim__, pSim00, pSim01, p->nWords );
272 Abc_TtOrAnd( pSim__, pSim10, pSim11, p->nWords );
273
274 Abc_TtAndSharp( pSim00, pSim00, pSim__, p->nWords, 1 );
275 Abc_TtAndSharp( pSim01, pSim01, pSim__, p->nWords, 1 );
276 Abc_TtAndSharp( pSim10, pSim10, pSim__, p->nWords, 1 );
277 Abc_TtAndSharp( pSim11, pSim11, pSim__, p->nWords, 1 );
278 }
279 }
280 return 1;
281}
282void Cec_ManSInsert( Cec_ManS_t * p, int iNode )
283{
284 Gia_Obj_t * pNode; int Level;
285 assert( iNode > 0 );
286 if ( Gia_ObjIsTravIdCurrentId(p->pAig, iNode) )
287 return;
288 Gia_ObjSetTravIdCurrentId(p->pAig, iNode);
289 pNode = Gia_ManObj( p->pAig, iNode );
290 if ( Gia_ObjIsCi(pNode) )
291 {
292 Vec_IntPush( p->vInputs, iNode );
293 return;
294 }
295 assert( Gia_ObjIsAnd(pNode) );
296 Level = Gia_ObjLevelId( p->pAig, iNode );
297 assert( Level > 0 );
298 Vec_WecPush( p->vLevels, Level, iNode );
299 p->nLevelMax = Abc_MaxInt( p->nLevelMax, Level );
300 p->nLevelMin = Abc_MinInt( p->nLevelMin, Level );
301 assert( p->nLevelMin <= p->nLevelMax );
302}
304{
305 Vec_Int_t * vLevel;
306 int i, k, iNode, fSolved = 0;
307 Vec_WecForEachLevelReverseStartStop( p->vLevels, vLevel, i, p->nLevelMax+1, p->nLevelMin )
308 {
309 Vec_IntForEachEntry( vLevel, iNode, k )
310 {
311 Gia_Obj_t * pNode = Gia_ManObj( p->pAig, iNode );
312 if ( !fSolved && Cec_ManSRunPropagate( p, iNode ) )
313 {
314 Cec_ManSInsert( p, Gia_ObjFaninId0(pNode, iNode) );
315 Cec_ManSInsert( p, Gia_ObjFaninId1(pNode, iNode) );
316 if ( Abc_TtIsConst1(Vec_WrdArray(p->vSims), p->nWords) )
317 fSolved = 1;
318 }
319 Abc_TtClear( Cec_ManSSim(p, iNode, 0), 2*p->nWords );
320 }
321 Vec_IntClear( vLevel );
322 }
323 //Vec_WecForEachLevel( p->vLevels, vLevel, i )
324 // assert( Vec_IntSize(vLevel) == 0 );
325 return fSolved;
326}
327int Cec_ManSRunSim( Cec_ManS_t * p, int iNode0, int iNode1 )
328{
329 abctime clk = Abc_Clock();
330 //Vec_Int_t * vLevel;
331 //int pNodes[2] = { iNode0, iNode1 };
332 int i, iNode, Status, fDiff = Gia_ObjPhaseDiff( p->pAig, iNode0, iNode1 );
333 word * pSim00 = Cec_ManSSim( p, iNode0, 0 );
334 word * pSim01 = Cec_ManSSim( p, iNode0, 1 );
335 word * pSim10 = Cec_ManSSim( p, iNode1, fDiff );
336 word * pSim11 = Cec_ManSSim( p, iNode1, !fDiff );
337 Abc_TtClear( Vec_WrdArray(p->vSims), p->nWords );
338 //for ( i = 0; i < Vec_WrdSize(p->vSims); i++ )
339 // assert( p->vSims->pArray[i] == 0 );
340 assert( Vec_IntSize(p->vInputs) == 0 );
341 if ( iNode0 == 0 )
342 Abc_TtFill( pSim11, p->nWords );
343 else
344 {
345 if ( p->nWords == 1 )
346 {
347 pSim00[0] = (word)0xFFFFFFFF;
348 pSim11[0] = (word)0xFFFFFFFF;
349 pSim01[0] = pSim00[0] << 32;
350 pSim10[0] = pSim11[0] << 32;
351 }
352 else
353 {
354 assert( p->nWords % 2 == 0 );
355 Abc_TtFill( pSim00, p->nWords/2 );
356 Abc_TtFill( pSim11, p->nWords/2 );
357 Abc_TtFill( pSim01 + p->nWords/2, p->nWords/2 );
358 Abc_TtFill( pSim10 + p->nWords/2, p->nWords/2 );
359 }
360 }
361 p->nLevelMin = ABC_INFINITY;
362 p->nLevelMax = 0;
363 Gia_ManIncrementTravId( p->pAig );
364 if ( iNode0 )
365 Cec_ManSInsert( p, iNode0 );
366 Cec_ManSInsert( p, iNode1 );
367 p->nSkipped = p->nVisited = 0;
368 Status = Cec_ManSRunSimInt( p );
369 if ( Status == 0 )
370 p->clkSat += Abc_Clock() - clk;
371 else
372 p->clkUnsat += Abc_Clock() - clk;
373// if ( Status == 0 )
374// printf( "Solving %6d and %6d. Skipped = %6d. Visited = %6d. Cone = %6d. Min = %3d. Max = %3d.\n",
375// iNode0, iNode1, p->nSkipped, p->nVisited, Gia_ManConeSize(p->pAig, pNodes, 2), p->nLevelMin, p->nLevelMax );
376 if ( Status == 0 )
377 Cec_ManSVerify( p, iNode0, iNode1 ), p->nCexes++;
378 Vec_IntForEachEntry( p->vInputs, iNode, i )
379 Abc_TtClear( Cec_ManSSim(p, iNode, 0), 2*p->nWords );
380 Vec_IntClear( p->vInputs );
381 return Status;
382}
384{
385 abctime clk = Abc_Clock();
386 Cec_ManS_t * p;
387 int i, k, nWords = 1;
388 Gia_ManRandomW( 1 );
389 p = Cec_ManSStart( pAig, nWords );
390 Gia_ManForEachClass0( p->pAig, i )
391 Gia_ClassForEachObj1( p->pAig, i, k )
392 Cec_ManSRunSim( p, i, k );
393 printf( "Detected %d CEXes. ", p->nCexes );
394 Abc_PrintTime( 1, "Time ", Abc_Clock() - clk );
395 Abc_PrintTime( 1, "Sat ", p->clkSat );
396 Abc_PrintTime( 1, "Unsat", p->clkUnsat );
397 Cec_ManSStop( p );
398}
399
400
404
405
407
int nWords
Definition abcNpn.c:127
ABC_INT64_T abctime
Definition abc_global.h:332
#define ABC_ALLOC(type, num)
Definition abc_global.h:264
#define ABC_INFINITY
MACRO DEFINITIONS ///.
Definition abc_global.h:250
#define ABC_FREE(obj)
Definition abc_global.h:267
#define ABC_NAMESPACE_IMPL_START
#define ABC_NAMESPACE_IMPL_END
typedefABC_NAMESPACE_IMPL_START struct Vec_Int_t_ Vec_Int_t
DECLARATIONS ///.
Definition bblif.c:37
void Cec_ManSRunTest(Gia_Man_t *pAig)
Definition cecSim.c:383
int Cec_ManSRunSimInt(Cec_ManS_t *p)
Definition cecSim.c:303
void Cec_ManSInsert(Cec_ManS_t *p, int iNode)
Definition cecSim.c:282
void Cec_ManSVerify(Cec_ManS_t *p, int iObj0, int iObj1)
Definition cecSim.c:134
int Cec_ManSRunSim(Cec_ManS_t *p, int iNode0, int iNode1)
Definition cecSim.c:327
int Cec_ManSRunPropagate(Cec_ManS_t *p, int iNode)
Definition cecSim.c:217
void Cec_ManSStop(Cec_ManS_t *p)
Definition cecSim.c:88
Cec_ManS_t * Cec_ManSStart(Gia_Man_t *pAig, int nWords)
FUNCTION DEFINITIONS ///.
Definition cecSim.c:71
void Cec_ManSRunImply(Cec_ManS_t *p, int iNode)
Definition cecSim.c:184
#define SIM_RANDS
DECLARATIONS ///.
Definition cecSim.c:32
int Cec_ManSVerify_rec(Gia_Man_t *p, int iObj)
Definition cecSim.c:108
struct Cec_ManS_t_ Cec_ManS_t
Definition cecSim.c:34
void Cec_ManSVerifyTwo(Gia_Man_t *p, int iObj0, int iObj1)
Definition cecSim.c:123
Cube * p
Definition exorList.c:222
word Gia_ManRandomW(int fReset)
Definition giaUtil.c:67
#define Gia_ClassForEachObj1(p, i, iObj)
Definition gia.h:1109
struct Gia_Obj_t_ Gia_Obj_t
Definition gia.h:76
struct Gia_Man_t_ Gia_Man_t
Definition gia.h:96
void Gia_ManIncrementTravId(Gia_Man_t *p)
Definition giaUtil.c:190
int Gia_ManLevelNum(Gia_Man_t *p)
Definition giaUtil.c:546
#define Gia_ManForEachClass0(p, i)
Definition gia.h:1103
unsigned __int64 word
DECLARATIONS ///.
Definition kitPerm.c:36
word * pTemp[4]
Definition cecSim.c:45
int nWords
Definition cecSim.c:37
Vec_Wec_t * vLevels
Definition cecSim.c:43
int nVisited
Definition cecSim.c:48
Vec_Wrd_t * vSims
Definition cecSim.c:44
int nLevelMin
Definition cecSim.c:39
int nSkipped
Definition cecSim.c:47
word Rands[SIM_RANDS]
Definition cecSim.c:46
Gia_Man_t * pAig
Definition cecSim.c:41
int nLevelMax
Definition cecSim.c:38
int nCexes
Definition cecSim.c:49
abctime clkSat
Definition cecSim.c:50
Vec_Int_t * vInputs
Definition cecSim.c:42
abctime clkUnsat
Definition cecSim.c:51
int iRand
Definition cecSim.c:40
unsigned fMark1
Definition gia.h:86
#define assert(ex)
Definition util_old.h:213
char * memset()
#define Vec_IntForEachEntry(vVec, Entry, i)
MACRO DEFINITIONS ///.
Definition vecInt.h:54
#define Vec_WecForEachLevelReverseStartStop(vGlob, vVec, i, LevelStart, LevelStop)
Definition vecWec.h:67
typedefABC_NAMESPACE_HEADER_START struct Vec_Wec_t_ Vec_Wec_t
INCLUDES ///.
Definition vecWec.h:42
typedefABC_NAMESPACE_HEADER_START struct Vec_Wrd_t_ Vec_Wrd_t
INCLUDES ///.
Definition vecWrd.h:42