ABC: A System for Sequential Synthesis and Verification
 
Loading...
Searching...
No Matches
fpgaTruth.c
Go to the documentation of this file.
1
18
19#include "fpgaInt.h"
20#include "bdd/cudd/cudd.h"
21
23
24
28
32
44DdNode * Fpga_TruthsCutBdd_rec( DdManager * dd, Fpga_Cut_t * pCut, Fpga_NodeVec_t * vVisited )
45{
46 DdNode * bFunc, * bFunc0, * bFunc1;
47 assert( !Fpga_IsComplement(pCut) );
48 // if the cut is visited, return the result
49 if ( pCut->uSign )
50 return (DdNode *)(ABC_PTRUINT_T)pCut->uSign;
51 // compute the functions of the children
52 bFunc0 = Fpga_TruthsCutBdd_rec( dd, Fpga_CutRegular(pCut->pOne), vVisited ); Cudd_Ref( bFunc0 );
53 bFunc0 = Cudd_NotCond( bFunc0, Fpga_CutIsComplement(pCut->pOne) );
54 bFunc1 = Fpga_TruthsCutBdd_rec( dd, Fpga_CutRegular(pCut->pTwo), vVisited ); Cudd_Ref( bFunc1 );
55 bFunc1 = Cudd_NotCond( bFunc1, Fpga_CutIsComplement(pCut->pTwo) );
56 // get the function of the cut
57 bFunc = Cudd_bddAnd( dd, bFunc0, bFunc1 ); Cudd_Ref( bFunc );
58 bFunc = Cudd_NotCond( bFunc, pCut->Phase );
59 Cudd_RecursiveDeref( dd, bFunc0 );
60 Cudd_RecursiveDeref( dd, bFunc1 );
61 assert( pCut->uSign == 0 );
62 pCut->uSign = (unsigned)(ABC_PTRUINT_T)bFunc;
63 // add this cut to the visited list
64 Fpga_NodeVecPush( vVisited, (Fpga_Node_t *)pCut );
65 return bFunc;
66}
67
79void * Fpga_TruthsCutBdd( void * dd, Fpga_Cut_t * pCut )
80{
81 Fpga_NodeVec_t * vVisited;
82 DdNode * bFunc;
83 int i;
84 assert( pCut->nLeaves > 1 );
85 // set the leaf variables
86 for ( i = 0; i < pCut->nLeaves; i++ )
87 pCut->ppLeaves[i]->pCuts->uSign = (unsigned)(ABC_PTRUINT_T)Cudd_bddIthVar( (DdManager *)dd, i );
88 // recursively compute the function
89 vVisited = Fpga_NodeVecAlloc( 10 );
90 bFunc = Fpga_TruthsCutBdd_rec( (DdManager *)dd, pCut, vVisited ); Cudd_Ref( bFunc );
91 // clean the intermediate BDDs
92 for ( i = 0; i < pCut->nLeaves; i++ )
93 pCut->ppLeaves[i]->pCuts->uSign = 0;
94 for ( i = 0; i < vVisited->nSize; i++ )
95 {
96 pCut = (Fpga_Cut_t *)vVisited->pArray[i];
97 Cudd_RecursiveDeref( (DdManager *)dd, (DdNode*)(ABC_PTRUINT_T)pCut->uSign );
98 pCut->uSign = 0;
99 }
100// printf( "%d ", vVisited->nSize );
101 Fpga_NodeVecFree( vVisited );
102 Cudd_Deref( bFunc );
103 return bFunc;
104}
105
106
119{
120 assert( !Fpga_IsComplement(pCut) );
121 if ( pCut->fMark )
122 return;
123 pCut->fMark = 1;
124 Fpga_CutVolume_rec( Fpga_CutRegular(pCut->pOne), vVisited );
125 Fpga_CutVolume_rec( Fpga_CutRegular(pCut->pTwo), vVisited );
126 Fpga_NodeVecPush( vVisited, (Fpga_Node_t *)pCut );
127}
128
141{
142 Fpga_NodeVec_t * vVisited;
143 int Volume, i;
144 assert( pCut->nLeaves > 1 );
145 // set the leaf variables
146 for ( i = 0; i < pCut->nLeaves; i++ )
147 pCut->ppLeaves[i]->pCuts->fMark = 1;
148 // recursively compute the function
149 vVisited = Fpga_NodeVecAlloc( 10 );
150 Fpga_CutVolume_rec( pCut, vVisited );
151 // clean the marks
152 for ( i = 0; i < pCut->nLeaves; i++ )
153 pCut->ppLeaves[i]->pCuts->fMark = 0;
154 for ( i = 0; i < vVisited->nSize; i++ )
155 {
156 pCut = (Fpga_Cut_t *)vVisited->pArray[i];
157 pCut->fMark = 0;
158 }
159 Volume = vVisited->nSize;
160 printf( "%d ", Volume );
161 Fpga_NodeVecFree( vVisited );
162 return Volume;
163}
164
168
169
171
#define ABC_NAMESPACE_IMPL_START
#define ABC_NAMESPACE_IMPL_END
#define Fpga_CutRegular(p)
Definition fpgaInt.h:74
Fpga_NodeVec_t * Fpga_NodeVecAlloc(int nCap)
FUNCTION DEFINITIONS ///.
Definition fpgaVec.c:45
void Fpga_NodeVecFree(Fpga_NodeVec_t *p)
Definition fpgaVec.c:68
#define Fpga_CutIsComplement(p)
Definition fpgaInt.h:73
void Fpga_NodeVecPush(Fpga_NodeVec_t *p, Fpga_Node_t *Entry)
Definition fpgaVec.c:169
int Fpga_CutVolume(Fpga_Cut_t *pCut)
Definition fpgaTruth.c:140
void * Fpga_TruthsCutBdd(void *dd, Fpga_Cut_t *pCut)
Definition fpgaTruth.c:79
ABC_NAMESPACE_IMPL_START DdNode * Fpga_TruthsCutBdd_rec(DdManager *dd, Fpga_Cut_t *pCut, Fpga_NodeVec_t *vVisited)
DECLARATIONS ///.
Definition fpgaTruth.c:44
void Fpga_CutVolume_rec(Fpga_Cut_t *pCut, Fpga_NodeVec_t *vVisited)
Definition fpgaTruth.c:118
struct Fpga_NodeStruct_t_ Fpga_Node_t
Definition fpga.h:44
struct Fpga_NodeVecStruct_t_ Fpga_NodeVec_t
Definition fpga.h:45
struct Fpga_CutStruct_t_ Fpga_Cut_t
Definition fpga.h:46
#define Fpga_IsComplement(p)
GLOBAL VARIABLES ///.
Definition fpga.h:57
Fpga_Node_t * ppLeaves[FPGA_MAX_LEAVES+1]
Definition fpgaInt.h:237
Fpga_Cut_t * pTwo
Definition fpgaInt.h:235
unsigned uSign
Definition fpgaInt.h:239
Fpga_Cut_t * pOne
Definition fpgaInt.h:234
Fpga_Cut_t * pCuts
Definition fpgaInt.h:224
Fpga_Node_t ** pArray
Definition fpgaInt.h:252
#define assert(ex)
Definition util_old.h:213