fretInit.c File Reference

#include "fretime.h"
#include "base/io/ioAbc.h"
#include "map/mio/mio.h"
#include "aig/hop/hop.h"

Include dependency graph for fretInit.c:

Go to the source code of this file.

Functions
void *	Abc_FrameReadLibGen ()
void	Abc_NtkMarkCone_rec (Abc_Obj_t *pObj, int fForward)
void	Abc_FlowRetime_InitState (Abc_Ntk_t *pNtk)
	FUNCTION DEFINITIONS ///.
void	Abc_FlowRetime_PrintInitStateInfo (Abc_Ntk_t *pNtk)
void	Abc_FlowRetime_UpdateForwardInit (Abc_Ntk_t *pNtk)
void	Abc_FlowRetime_SetupBackwardInit (Abc_Ntk_t *pNtk)
int	Abc_FlowRetime_SolveBackwardInit (Abc_Ntk_t *pNtk)
void	Abc_FlowRetime_UpdateBackwardInit (Abc_Ntk_t *pNtk)
Abc_Obj_t *	Abc_FlowRetime_CopyNodeToInitNtk (Abc_Obj_t *pOrigObj)
int	Abc_FlowRetime_PartialSat (Vec_Ptr_t *vNodes, int cut)
void	Abc_FlowRetime_ConstrainInit ()
void	Abc_FlowRetime_RemoveInitBias ()
void	Abc_FlowRetime_AddInitBias ()

Function Documentation

Abc_FlowRetime_AddInitBias()

void Abc_FlowRetime_AddInitBias

(

)

Function*************************************************************

Synopsis [Adds nodes to bias against uninitializable cuts.]

Description []

SideEffects []

SeeAlso []

Definition at line 1218 of file fretInit.c.

                                   {
  Abc_Ntk_t *pNtk = pManMR->pNtk;
  Abc_Obj_t *pBiasNode, *pObj;
  InitConstraint_t *pConstraint;
  int i, j, id;
  const int nConstraints = Vec_PtrSize( pManMR->vInitConstraints );
 
  pManMR->pDataArray = ABC_REALLOC( Flow_Data_t, pManMR->pDataArray, pManMR->nNodes + (nConstraints*(pManMR->iteration+1)) );
  memset(pManMR->pDataArray + pManMR->nNodes, 0, sizeof(Flow_Data_t)*(nConstraints*(pManMR->iteration+1)));
 
  vprintf("\t\tcreating %d bias structures\n", nConstraints);
 
  Vec_PtrForEachEntry(InitConstraint_t*, pManMR->vInitConstraints, pConstraint, i ) {
    if (pConstraint->pBiasNode) continue;
    
 //   printf("\t\t\tbias %d...\n", i);
    pBiasNode = Abc_NtkCreateBlackbox( pNtk );
 
    Vec_IntForEachEntry( &pConstraint->vNodes, id, j ) {
      pObj = Abc_NtkObj(pNtk, id);
      Abc_FlowRetime_ConnectBiasNode(pBiasNode, pObj, Vec_IntEntry(&pConstraint->vLags, j));
    }
 
    // pConstraint->pBiasNode = pBiasNode;
  }
}

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Abc_FlowRetime_ConstrainInit()

void Abc_FlowRetime_ConstrainInit

(

)

Function*************************************************************

Synopsis [Constrains backward retiming for initializability.]

Description []

SideEffects []

SeeAlso []

Definition at line 1023 of file fretInit.c.

                                     {
  Vec_Ptr_t *vNodes;
  int low, high, mid;
  int i, n, lag;
  Abc_Obj_t *pObj = NULL, *pOrigObj;
  InitConstraint_t *pConstraint = ABC_ALLOC( InitConstraint_t, 1 );
 
  memset( pConstraint, 0, sizeof(InitConstraint_t) );
 
  assert(pManMR->pInitNtk);
 
  vprintf("\tsearch for initial state conflict...\n");
 
  vNodes = Abc_NtkDfs(pManMR->pInitNtk, 0);
  n = Vec_PtrSize(vNodes);
  // also add PIs to vNodes
  Abc_NtkForEachPi(pManMR->pInitNtk, pObj, i) 
    Vec_PtrPush(vNodes, pObj);
  Vec_PtrReorder(vNodes, n);
 
#if defined(DEBUG_CHECK)
    assert(!Abc_FlowRetime_PartialSat( vNodes, 0 ));
#endif
 
  // grow initialization constraint
  do {
    vprintf("\t\t");
 
    // find element to add to set...
    low = 0, high = Vec_PtrSize(vNodes);
    while (low != high-1) {
      mid = (low + high) >> 1;
      
      if (!Abc_FlowRetime_PartialSat( vNodes, mid )) {
        low = mid;
        vprintf("-");
      } else {
        high = mid;
        vprintf("*");
      }
      fflush(stdout);
    }
      
#if defined(DEBUG_CHECK)
    assert(Abc_FlowRetime_PartialSat( vNodes, high ));
    assert(!Abc_FlowRetime_PartialSat( vNodes, low ));
#endif
    
    // mark its TFO
    pObj = (Abc_Obj_t*)Vec_PtrEntry( vNodes, low );
    Abc_NtkMarkCone_rec( pObj, 1 );
    vprintf("   conflict term = %d ", low);
 
#if 0
    printf("init ------\n");
    Abc_ObjPrint(stdout, pObj);
    printf("\n");
    Abc_ObjPrintNeighborhood( pObj, 1 );
    printf("------\n");
#endif
 
    // add node to constraint
    Abc_FlowRetime_GetInitToOrig( pObj, &pOrigObj, &lag );
    assert(pOrigObj);
    vprintf(" <=> %d/%d\n", Abc_ObjId(pOrigObj), lag);
 
#if 0    
    printf("orig ------\n");
    Abc_ObjPrint(stdout, pOrigObj);
    printf("\n");
    Abc_ObjPrintNeighborhood( pOrigObj, 1 );
    printf("------\n");
#endif
    Vec_IntPush( &pConstraint->vNodes, Abc_ObjId(pOrigObj) );
    Vec_IntPush( &pConstraint->vLags, lag );
 
  } while (Abc_FlowRetime_PartialSat( vNodes, Vec_PtrSize(vNodes) ));
 
  pConstraint->pBiasNode = NULL;
 
  // add constraint
  Vec_PtrPush( pManMR->vInitConstraints, pConstraint );
 
  // clear marks
  Abc_NtkForEachObj( pManMR->pInitNtk, pObj, i)
    pObj->fMarkA = 0;
 
  // free
  Vec_PtrFree( vNodes );
}

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Abc_FlowRetime_CopyNodeToInitNtk()

Abc_Obj_t * Abc_FlowRetime_CopyNodeToInitNtk

(

Abc_Obj_t *

pOrigObj

)

Function*************************************************************

Synopsis [Creates a corresponding node in the init state network]

Description []

SideEffects []

SeeAlso []

Definition at line 737 of file fretInit.c.

                                                                   {
  Abc_Ntk_t *pNtk = pManMR->pNtk;
  Abc_Ntk_t *pInitNtk = pManMR->pInitNtk;
  Abc_Obj_t *pInitObj;
  void *pData;
  int fCompl[2];
 
  assert(pOrigObj);
 
  // what we do depends on the ntk types of original / init networks...
  
  // (0) convert BI/BO nodes to buffers
  if (Abc_ObjIsBi( pOrigObj ) || Abc_ObjIsBo( pOrigObj ) ) {
    pInitObj =  Abc_NtkCreateNodeBuf( pInitNtk, NULL );
    Abc_FlowRetime_ClearInitToOrig( pInitObj );
    return pInitObj;
  }
 
  // (i) strash node -> SOP node
  if (Abc_NtkIsStrash( pNtk )) {
 
    if (Abc_AigNodeIsConst( pOrigObj )) {
      return Abc_NtkCreateNodeConst1( pInitNtk );
    }
    if (!Abc_ObjIsNode( pOrigObj )) {
      assert(Abc_ObjFaninNum(pOrigObj) == 1);
      pInitObj =  Abc_NtkCreateNodeBuf( pInitNtk, NULL );
      Abc_FlowRetime_ClearInitToOrig( pInitObj );
      return pInitObj;
    }
 
    assert( Abc_ObjIsNode(pOrigObj) );
    pInitObj = Abc_NtkCreateObj( pInitNtk, ABC_OBJ_NODE );
    
    fCompl[0] = pOrigObj->fCompl0 ? 1 : 0;
    fCompl[1] = pOrigObj->fCompl1 ? 1 : 0;
    
    pData =  Abc_SopCreateAnd( (Mem_Flex_t *)pInitNtk->pManFunc, 2, fCompl );
    assert(pData);
    pInitObj->pData = Abc_SopRegister( (Mem_Flex_t *)pInitNtk->pManFunc, (const char*)pData );
  } 
 
  // (ii) mapped node -> SOP node
  else if (Abc_NtkHasMapping( pNtk )) {
    if (!pOrigObj->pData) {
      // assume terminal...
      assert(Abc_ObjFaninNum(pOrigObj) == 1);
 
      pInitObj =  Abc_NtkCreateNodeBuf( pInitNtk, NULL );
      Abc_FlowRetime_ClearInitToOrig( pInitObj );
      return pInitObj;
    }
 
    pInitObj = Abc_NtkCreateObj( pInitNtk, (Abc_ObjType_t)Abc_ObjType(pOrigObj) );
    pData = Mio_GateReadSop((Mio_Gate_t*)pOrigObj->pData);
    assert( Abc_SopGetVarNum((char*)pData) == Abc_ObjFaninNum(pOrigObj) );
    
    pInitObj->pData = Abc_SopRegister( (Mem_Flex_t *)pInitNtk->pManFunc, (const char*)pData );
  } 
 
  // (iii) otherwise, duplicate obj
  else {
    pInitObj = Abc_NtkDupObj( pInitNtk, pOrigObj, 0 );
    
    // copy phase
    pInitObj->fPhase = pOrigObj->fPhase;
  }
 
  assert(pInitObj);
  return pInitObj;
}

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Abc_FlowRetime_InitState()

void Abc_FlowRetime_InitState

(

Abc_Ntk_t *

pNtk

)

FUNCTION DEFINITIONS ///.

Function*************************************************************

Synopsis [Updates initial state information.]

Description [Assumes latch boxes in original position, latches in new positions.]

SideEffects []

SeeAlso []

Definition at line 75 of file fretInit.c.

                                             {
 
  if (!pManMR->fComputeInitState) return;
 
  if (pManMR->fIsForward)
    Abc_FlowRetime_UpdateForwardInit( pNtk );
  else {
    Abc_FlowRetime_UpdateBackwardInit( pNtk );
  }
}

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Abc_FlowRetime_PartialSat()

int Abc_FlowRetime_PartialSat	(	Vec_Ptr_t *	vNodes,
		int	cut )

Function*************************************************************

Synopsis [Constrains backward retiming for initializability.]

Description []

SideEffects []

SeeAlso []

Definition at line 956 of file fretInit.c.

                                                          {
  Abc_Ntk_t *pPartNtk, *pInitNtk = pManMR->pInitNtk;
  Abc_Obj_t *pObj, *pNext, *pPartObj, *pPartNext, *pPo;
  int i, j, result;
 
  assert( Abc_NtkPoNum( pInitNtk ) == 1 );
 
  pPartNtk = Abc_NtkAlloc( pInitNtk->ntkType, pInitNtk->ntkFunc, 0 );
 
  // copy network
  Vec_PtrForEachEntry( Abc_Obj_t *, vNodes, pObj, i ) {
    pObj->Level = i;
    assert(!Abc_ObjIsPo( pObj ));
 
    if (i < cut && !pObj->fMarkA) {
      pPartObj = Abc_NtkCreatePi( pPartNtk );
      Abc_ObjSetCopy( pObj, pPartObj );
    } else {
      // copy node
      pPartObj = Abc_NtkDupObj( pPartNtk, pObj, 0 );
      // copy complementation
      pPartObj->fPhase = pObj->fPhase;
   
      // connect fanins
      Abc_ObjForEachFanin( pObj, pNext, j ) {   
        pPartNext = Abc_ObjCopy( pNext );
        assert(pPartNext);
        Abc_ObjAddFanin( pPartObj, pPartNext );
      }
    }
 
    assert(pObj->pCopy == pPartObj);
  }
  
  // create PO
  pPo = Abc_NtkCreatePo( pPartNtk );
  pNext = Abc_ObjFanin0( Abc_NtkPo( pInitNtk, 0 ) );
  pPartNext = Abc_ObjCopy( pNext );
  assert( pPartNext );
  Abc_ObjAddFanin( pPo, pPartNext );
  
  // check network
#if defined(DEBUG_CHECK)
  Abc_NtkAddDummyPoNames(pPartNtk);
  Abc_NtkAddDummyPiNames(pPartNtk);
  Abc_NtkCheck( pPartNtk );
#endif
 
  result = Abc_NtkMiterSat( pPartNtk, (ABC_INT64_T)500000, (ABC_INT64_T)50000000, 0, NULL, NULL );
 
  Abc_NtkDelete( pPartNtk );
 
  return !result;
}

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Abc_FlowRetime_PrintInitStateInfo()

void Abc_FlowRetime_PrintInitStateInfo

(

Abc_Ntk_t *

pNtk

)

Function*************************************************************

Synopsis [Prints initial state information.]

Description [Prints distribution of 0,1,and X initial states.]

SideEffects []

SeeAlso []

Definition at line 133 of file fretInit.c.

                                                      {
  int i, n0=0, n1=0, nDC=0, nOther=0;
  Abc_Obj_t *pLatch;
 
  Abc_NtkForEachLatch( pNtk, pLatch, i ) {
    if (Abc_LatchIsInit0(pLatch)) n0++;
    else if (Abc_LatchIsInit1(pLatch)) n1++;
    else if (Abc_LatchIsInitDc(pLatch)) nDC++;
    else nOther++;
  }     
 
  printf("\tinitial states {0,1,x} = {%d, %d, %d}", n0, n1, nDC);
  if (nOther)
    printf(" + %d UNKNOWN", nOther);
  printf("\n");
}

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Abc_FlowRetime_RemoveInitBias()

void Abc_FlowRetime_RemoveInitBias

(

)

Function*************************************************************

Synopsis [Removes nodes to bias against uninitializable cuts.]

Description []

SideEffects []

SeeAlso []

Definition at line 1126 of file fretInit.c.

                                      {
  // Abc_Ntk_t *pNtk = pManMR->pNtk;
  Abc_Obj_t *pBiasNode;
  InitConstraint_t *pConstraint;
  int i;
 
  Vec_PtrForEachEntry( InitConstraint_t *, pManMR->vInitConstraints, pConstraint, i ) {
    pBiasNode = pConstraint->pBiasNode;
    pConstraint->pBiasNode = NULL;
 
    if (pBiasNode)
      Abc_NtkDeleteObj(pBiasNode);
  }
}

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Abc_FlowRetime_SetupBackwardInit()

void Abc_FlowRetime_SetupBackwardInit

(

Abc_Ntk_t *

pNtk

)

Function*************************************************************

Synopsis [Sets up backward initial state computation.]

Description []

SideEffects []

SeeAlso []

Definition at line 489 of file fretInit.c.

                                                          {
  Abc_Obj_t *pLatch, *pObj, *pPi;
  int i;
  Vec_Ptr_t *vObj = Vec_PtrAlloc(100);
 
  // create the network used for the initial state computation
  if (Abc_NtkIsStrash(pNtk)) {
    pManMR->pInitNtk = Abc_NtkAlloc( ABC_NTK_LOGIC, ABC_FUNC_SOP, 1 );
  } else if (Abc_NtkHasMapping(pNtk))
    pManMR->pInitNtk = Abc_NtkAlloc( pNtk->ntkType, ABC_FUNC_SOP, 1 );
  else
    pManMR->pInitNtk = Abc_NtkAlloc( pNtk->ntkType, pNtk->ntkFunc, 1 );
 
  // mitre inputs
  Abc_NtkForEachLatch( pNtk, pLatch, i ) {
    // map latch to initial state network
    pPi = Abc_NtkCreatePi( pManMR->pInitNtk );
 
    // DEBUG
    // printf("setup : mapping latch %d to PI %d\n", pLatch->Id, pPi->Id);
 
    // has initial state requirement?
    if (Abc_LatchIsInit0(pLatch)) {
      pObj = Abc_NtkCreateNodeInv( pManMR->pInitNtk, pPi );
      Vec_PtrPush(vObj, pObj);
    }
    else if (Abc_LatchIsInit1(pLatch)) {
      Vec_PtrPush(vObj, pPi);
    }
    
    Abc_ObjSetData( pLatch, pPi );     // if not verifying init state
    // FDATA(pLatch)->pInitObj = pPi;  // if verifying init state
  }
 
  // are there any nodes not DC?
  if (!Vec_PtrSize(vObj)) {
    pManMR->fSolutionIsDc = 1;
    return;
  } else 
    pManMR->fSolutionIsDc = 0;
 
  // mitre output
 
  // create n-input AND gate
  pObj = Abc_NtkCreateNodeAnd( pManMR->pInitNtk, vObj );
 
  Abc_ObjAddFanin( Abc_NtkCreatePo( pManMR->pInitNtk ), pObj );
 
  Vec_PtrFree( vObj );
}

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Abc_FlowRetime_SolveBackwardInit()

int Abc_FlowRetime_SolveBackwardInit

(

Abc_Ntk_t *

pNtk

)

Function*************************************************************

Synopsis [Solves backward initial state computation.]

Description []

SideEffects [Sets object copies in init ntk.]

SeeAlso []

Definition at line 552 of file fretInit.c.

                                                         {
  int i;
  Abc_Obj_t *pObj, *pInitObj;
  Vec_Ptr_t *vDelete = Vec_PtrAlloc(0);
  Abc_Ntk_t *pSatNtk;
  int result;
 
  assert(pManMR->pInitNtk);
 
  // is the solution entirely DC's?
  if (pManMR->fSolutionIsDc) {
    Vec_PtrFree(vDelete);
    Abc_NtkForEachLatch( pNtk, pObj, i ) Abc_LatchSetInitDc( pObj );
    vprintf("\tno init state computation: all-don't-care solution\n");
    return 1;
  }
 
  // check that network is combinational
  Abc_NtkForEachObj( pManMR->pInitNtk, pObj, i ) {
    assert(!Abc_ObjIsLatch(pObj));
    assert(!Abc_ObjIsBo(pObj));
    assert(!Abc_ObjIsBi(pObj));
  }
  
  // delete superfluous nodes
  while(Vec_PtrSize( vDelete )) {
    pObj = (Abc_Obj_t *)Vec_PtrPop( vDelete );
    Abc_NtkDeleteObj( pObj );
  }
  Vec_PtrFree(vDelete);
 
  // do some final cleanup on the network
  Abc_NtkAddDummyPoNames(pManMR->pInitNtk);
  Abc_NtkAddDummyPiNames(pManMR->pInitNtk);
  if (Abc_NtkIsLogic(pManMR->pInitNtk))
    Abc_NtkCleanup(pManMR->pInitNtk, 0);
 
#if defined(DEBUG_PRINT_INIT_NTK)
  Abc_NtkLevelReverse( pManMR->pInitNtk );
  Abc_NtkForEachObj( pManMR->pInitNtk, pObj, i ) 
    if (Abc_ObjLevel( pObj ) < 2)
      Abc_ObjPrint(stdout, pObj);
#endif
  
  vprintf("\tsolving for init state (%d nodes)... ", Abc_NtkObjNum(pManMR->pInitNtk));
  fflush(stdout);
#ifdef ABC_USE_CUDD
  // convert SOPs to BDD
  if (Abc_NtkHasSop(pManMR->pInitNtk))
    Abc_NtkSopToBdd( pManMR->pInitNtk );
  // convert AIGs to BDD
  if (Abc_NtkHasAig(pManMR->pInitNtk))
    Abc_NtkAigToBdd( pManMR->pInitNtk );
#else
  // convert SOPs to AIG
  if (Abc_NtkHasSop(pManMR->pInitNtk))
    Abc_NtkSopToAig( pManMR->pInitNtk );
#endif
  pSatNtk = pManMR->pInitNtk;
  
  // solve
  result = Abc_NtkMiterSat( pSatNtk, (ABC_INT64_T)500000, (ABC_INT64_T)50000000, 0, NULL, NULL );
 
  if (!result) { 
    vprintf("SUCCESS\n");
  } else  {    
    vprintf("FAILURE\n");
    return 0;
  }
 
  // clear initial values, associate PIs to latches
  Abc_NtkForEachPi( pManMR->pInitNtk, pInitObj, i ) Abc_ObjSetCopy( pInitObj, NULL );
  Abc_NtkForEachLatch( pNtk, pObj, i ) {
    pInitObj = (Abc_Obj_t*)Abc_ObjData( pObj );
    assert( Abc_ObjIsPi( pInitObj ));
    Abc_ObjSetCopy( pInitObj, pObj );
    Abc_LatchSetInitNone( pObj );
 
    // DEBUG
    // printf("solve : getting latch %d from PI %d\n", pObj->Id, pInitObj->Id);
  }
 
  // copy solution from PIs to latches
  assert(pManMR->pInitNtk->pModel);
  Abc_NtkForEachPi( pManMR->pInitNtk, pInitObj, i ) {
    if ((pObj = Abc_ObjCopy( pInitObj ))) {
      if ( pManMR->pInitNtk->pModel[i] )
        Abc_LatchSetInit1( pObj );
      else
        Abc_LatchSetInit0( pObj );
    }
  }
 
#if defined(DEBUG_CHECK)
  // check that all latches have initial state
  Abc_NtkForEachLatch( pNtk, pObj, i ) assert( !Abc_LatchIsInitNone( pObj ) );
#endif
 
  return 1;
}

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Abc_FlowRetime_UpdateBackwardInit()

void Abc_FlowRetime_UpdateBackwardInit

(

Abc_Ntk_t *

pNtk

)

Function*************************************************************

Synopsis [Updates backward initial state computation problem.]

Description [Assumes box outputs in old positions stored w/ init values.]

SideEffects []

SeeAlso []

Definition at line 665 of file fretInit.c.

                                                           {
  Abc_Obj_t *pOrigObj,  *pInitObj;
  Vec_Ptr_t *vBo = Vec_PtrAlloc(100);
  Vec_Ptr_t *vPi = Vec_PtrAlloc(100);
  Abc_Ntk_t *pInitNtk = pManMR-> pInitNtk;
  Abc_Obj_t *pBuf;
  int i;
 
  // remove PIs from network (from BOs)
  Abc_NtkForEachObj( pNtk, pOrigObj, i )
    if (Abc_ObjIsBo(pOrigObj)) {
      pInitObj = FDATA(pOrigObj)->pInitObj;
      assert(Abc_ObjIsPi(pInitObj));
 
      // DEBUG
      // printf("update : freeing PI %d\n", pInitObj->Id);
      
      // create a buffer instead
      pBuf = Abc_NtkCreateNodeBuf( pInitNtk, NULL );
      Abc_FlowRetime_ClearInitToOrig( pBuf );
 
      Abc_ObjBetterTransferFanout( pInitObj, pBuf, 0 );
      FDATA(pOrigObj)->pInitObj = pBuf;
      pOrigObj->fMarkA = 1;
 
      Vec_PtrPush(vBo, pOrigObj);
      Vec_PtrPush(vPi, pInitObj);
    }
  
  // check that PIs are all free
  Abc_NtkForEachPi( pInitNtk, pInitObj, i) {
    assert( Abc_ObjFanoutNum( pInitObj ) == 0);
  }
 
  // add PIs to to latches
  Abc_NtkForEachLatch( pNtk, pOrigObj, i ) {
    assert(Vec_PtrSize(vPi) > 0);
    pInitObj = (Abc_Obj_t*)Vec_PtrPop(vPi);
 
    // DEBUG
    // printf("update : mapping latch %d to PI %d\n", pOrigObj->Id, pInitObj->Id);
 
    pOrigObj->fMarkA = pOrigObj->fMarkB = 1;
    FDATA(pOrigObj)->pInitObj = pInitObj;
    Abc_ObjSetData(pOrigObj, pInitObj);
  }  
 
  // recursively build init network
  Vec_PtrForEachEntry( Abc_Obj_t *, vBo, pOrigObj, i )
    Abc_FlowRetime_UpdateBackwardInit_rec( pOrigObj );
  
  // clear flags
  Abc_NtkForEachObj( pNtk, pOrigObj, i )
    pOrigObj->fMarkA = pOrigObj->fMarkB = 0;
 
  // deallocate
  Vec_PtrFree( vBo );
  Vec_PtrFree( vPi );
}

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Abc_FlowRetime_UpdateForwardInit()

void Abc_FlowRetime_UpdateForwardInit

(

Abc_Ntk_t *

pNtk

)

Function*************************************************************

Synopsis [Computes initial state after forward retiming.]

Description [Assumes box outputs in old positions stored w/ init values. Uses three-value simulation to preserve don't cares.]

SideEffects []

SeeAlso []

Definition at line 163 of file fretInit.c.

                                                          {
  Abc_Obj_t *pObj, *pFanin;
  int i;
 
  vprintf("\t\tupdating init state\n");
 
  Abc_NtkIncrementTravId( pNtk );
 
  Abc_NtkForEachLatch( pNtk, pObj, i ) {
    pFanin = Abc_ObjFanin0(pObj);
    Abc_FlowRetime_UpdateForwardInit_rec( pFanin );
 
    if (FTEST(pFanin, INIT_0))
      Abc_LatchSetInit0( pObj );
    else if (FTEST(pFanin, INIT_1))
      Abc_LatchSetInit1( pObj );
    else
      Abc_LatchSetInitDc( pObj );
  }
}

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Abc_FrameReadLibGen()

void * Abc_FrameReadLibGen ( )

extern

Definition at line 59 of file mainFrame.c.

{ return s_GlobalFrame->pLibGen;      } 

Abc_NtkMarkCone_rec()

void Abc_NtkMarkCone_rec ( Abc_Obj_t * pObj, int fForward )

extern

Function*************************************************************

Synopsis [Marks the cone with MarkA.]

Description []

SideEffects []

SeeAlso []

Definition at line 147 of file retArea.c.

{
    Abc_Obj_t * pNext;
    int i;
    if ( pObj->fMarkA )
        return;
    pObj->fMarkA = 1;
    if ( fForward )
    {
        Abc_ObjForEachFanout( pObj, pNext, i )
            Abc_NtkMarkCone_rec( pNext, fForward );
    }
    else
    {
        Abc_ObjForEachFanin( pObj, pNext, i )
            Abc_NtkMarkCone_rec( pNext, fForward );
    }
}

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