ABC: A System for Sequential Synthesis and Verification
 
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ioWriteVerilog.c File Reference
#include "ioAbc.h"
#include "base/main/main.h"
#include "map/mio/mio.h"
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Functions

void Io_WriteVerilog (Abc_Ntk_t *pNtk, char *pFileName, int fOnlyAnds, int fNewInterface)
 FUNCTION DEFINITIONS ///.
 
void Io_WriteLutModule (FILE *pFile, int nLutSize)
 
void Io_WriteFixedModules (FILE *pFile)
 
void Io_WriteVerilogObjectsLut (FILE *pFile, Abc_Ntk_t *pNtk, int nLutSize, int fFixed)
 
void Io_WriteVerilogLutInt (FILE *pFile, Abc_Ntk_t *pNtk, int nLutSize, int fFixed, int fNewInterface)
 
void Io_WriteVerilogLut (Abc_Ntk_t *pNtk, char *pFileName, int nLutSize, int fFixed, int fNoModules, int fNewInterface)
 

Function Documentation

◆ Io_WriteFixedModules()

void Io_WriteFixedModules ( FILE * pFile)

Definition at line 743 of file ioWriteVerilog.c.

744{
745 fprintf( pFile, "module LUT6 #( parameter INIT = 64\'h0000000000000000 ) (\n" );
746 fprintf( pFile, " output O,\n" );
747 fprintf( pFile, " input I0,\n" );
748 fprintf( pFile, " input I1,\n" );
749 fprintf( pFile, " input I2,\n" );
750 fprintf( pFile, " input I3,\n" );
751 fprintf( pFile, " input I4,\n" );
752 fprintf( pFile, " input I5\n" );
753 fprintf( pFile, ");\n" );
754 fprintf( pFile, " assign O = INIT[ {I5, I4, I3, I2, I1, I0} ];\n" );
755 fprintf( pFile, "endmodule\n\n" );
756
757 fprintf( pFile, "module MUXF7 (\n" );
758 fprintf( pFile, " output O,\n" );
759 fprintf( pFile, " input I0,\n" );
760 fprintf( pFile, " input I1,\n" );
761 fprintf( pFile, " input S\n" );
762 fprintf( pFile, ");\n" );
763 fprintf( pFile, " assign O = S ? I1 : I0;\n" );
764 fprintf( pFile, "endmodule\n\n" );
765
766 fprintf( pFile, "module MUXF8 (\n" );
767 fprintf( pFile, " output O,\n" );
768 fprintf( pFile, " input I0,\n" );
769 fprintf( pFile, " input I1,\n" );
770 fprintf( pFile, " input S\n" );
771 fprintf( pFile, ");\n" );
772 fprintf( pFile, " assign O = S ? I1 : I0;\n" );
773 fprintf( pFile, "endmodule\n\n" );
774}
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◆ Io_WriteLutModule()

void Io_WriteLutModule ( FILE * pFile,
int nLutSize )

Function*************************************************************

Synopsis [Write the network of K-input LUTs.]

Description []

SideEffects []

SeeAlso []

Definition at line 737 of file ioWriteVerilog.c.

738{
739 fprintf( pFile, "module lut%d #( parameter TT = %d\'h0 ) ( input [%d:0] in, output out );\n", nLutSize, 1<<nLutSize, nLutSize-1 );
740 fprintf( pFile, " assign out = TT[in];\n" );
741 fprintf( pFile, "endmodule\n\n" );
742}
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◆ Io_WriteVerilog()

void Io_WriteVerilog ( Abc_Ntk_t * pNtk,
char * pFileName,
int fOnlyAnds,
int fNewInterface )

FUNCTION DEFINITIONS ///.

Function*************************************************************

Synopsis [Write verilog.]

Description []

SideEffects []

SeeAlso []

Definition at line 58 of file ioWriteVerilog.c.

59{
60 Abc_Ntk_t * pNetlist;
61 FILE * pFile;
62 int i;
63
64 // can only write nodes represented using local AIGs
65 if ( !Abc_NtkIsAigNetlist(pNtk) && !Abc_NtkIsMappedNetlist(pNtk) )
66 {
67 printf( "Io_WriteVerilog(): Can produce Verilog for mapped or AIG netlists only.\n" );
68 return;
69 }
70 // start the output stream
71 pFile = fopen( pFileName, "w" );
72 if ( pFile == NULL )
73 {
74 fprintf( stdout, "Io_WriteVerilog(): Cannot open the output file \"%s\".\n", pFileName );
75 return;
76 }
77
78 // write the equations for the network
79 fprintf( pFile, "// Benchmark \"%s\" written by ABC on %s\n", pNtk->pName, Extra_TimeStamp() );
80 fprintf( pFile, "\n" );
81
82 // write modules
83 if ( pNtk->pDesign )
84 {
85 // write the network first
86 Io_WriteVerilogInt( pFile, pNtk, fOnlyAnds, fNewInterface );
87 // write other things
88 Vec_PtrForEachEntry( Abc_Ntk_t *, pNtk->pDesign->vModules, pNetlist, i )
89 {
90 assert( Abc_NtkIsNetlist(pNetlist) );
91 if ( pNetlist == pNtk )
92 continue;
93 fprintf( pFile, "\n" );
94 Io_WriteVerilogInt( pFile, pNetlist, fOnlyAnds, fNewInterface );
95 }
96 }
97 else
98 {
99 Io_WriteVerilogInt( pFile, pNtk, fOnlyAnds, fNewInterface );
100 }
101
102 fprintf( pFile, "\n" );
103 fclose( pFile );
104}
Abc_Ntk_t
struct Abc_Ntk_t_ Abc_Ntk_t
Definition abc.h:115
Extra_TimeStamp
char * Extra_TimeStamp()
Definition extraUtilFile.c:465
Abc_Des_t_::vModules
Vec_Ptr_t * vModules
Definition abc.h:225
Abc_Ntk_t_::pName
char * pName
Definition abc.h:158
Abc_Ntk_t_::pDesign
Abc_Des_t * pDesign
Definition abc.h:180
assert
#define assert(ex)
Definition util_old.h:213
Vec_PtrForEachEntry
#define Vec_PtrForEachEntry(Type, vVec, pEntry, i)
MACRO DEFINITIONS ///.
Definition vecPtr.h:55
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◆ Io_WriteVerilogLut()

void Io_WriteVerilogLut ( Abc_Ntk_t * pNtk,
char * pFileName,
int nLutSize,
int fFixed,
int fNoModules,
int fNewInterface )

Definition at line 923 of file ioWriteVerilog.c.

924{
925 FILE * pFile;
926 Abc_Ntk_t * pNtkTemp;
927 Abc_Obj_t * pObj;
928 int i, Counter = 0;
929 Abc_NtkForEachNode( pNtk, pObj, i )
930 if ( Abc_ObjFaninNum(pObj) > nLutSize )
931 {
932 if ( Counter < 3 )
933 printf( "Node \"%s\" has the fanin count (%d) larger than the LUT size (%d).\n", Abc_ObjName(pObj), Abc_ObjFaninNum(pObj), nLutSize );
934 Counter++;
935 }
936 if ( Counter )
937 {
938 printf( "In total, %d internal logic nodes exceed the fanin count limit. Verilog is not written.\n", Counter );
939 return;
940 }
941
942 // start the output stream
943 pFile = fopen( pFileName, "w" );
944 if ( pFile == NULL )
945 {
946 fprintf( stdout, "Io_WriteVerilog(): Cannot open the output file \"%s\".\n", pFileName );
947 return;
948 }
949
950 // write the equations for the network
951 fprintf( pFile, "// Benchmark \"%s\" written by ABC on %s\n", pNtk->pName, Extra_TimeStamp() );
952 fprintf( pFile, "\n" );
953 if ( !fNoModules )
954 {
955 if ( fFixed )
956 Io_WriteFixedModules( pFile );
957 else
958 Io_WriteLutModule( pFile, nLutSize );
959 }
960 pNtkTemp = Abc_NtkToNetlist( pNtk );
961 Abc_NtkToSop( pNtkTemp, -1, ABC_INFINITY );
962 Io_WriteVerilogLutInt( pFile, pNtkTemp, nLutSize, fFixed, fNewInterface );
963 Abc_NtkDelete( pNtkTemp );
964
965 fprintf( pFile, "\n" );
966 fclose( pFile );
967}
Abc_Obj_t
struct Abc_Obj_t_ Abc_Obj_t
Definition abc.h:116
Abc_ObjName
ABC_DLL char * Abc_ObjName(Abc_Obj_t *pNode)
DECLARATIONS ///.
Definition abcNames.c:49
Abc_NtkToNetlist
ABC_DLL Abc_Ntk_t * Abc_NtkToNetlist(Abc_Ntk_t *pNtk)
Definition abcNetlist.c:100
Abc_NtkToSop
ABC_DLL int Abc_NtkToSop(Abc_Ntk_t *pNtk, int fMode, int nCubeLimit)
Definition abcFunc.c:1261
Abc_NtkDelete
ABC_DLL void Abc_NtkDelete(Abc_Ntk_t *pNtk)
Definition abcNtk.c:1421
Abc_NtkForEachNode
#define Abc_NtkForEachNode(pNtk, pNode, i)
Definition abc.h:464
ABC_INFINITY
#define ABC_INFINITY
MACRO DEFINITIONS ///.
Definition abc_global.h:250
Io_WriteVerilogLutInt
void Io_WriteVerilogLutInt(FILE *pFile, Abc_Ntk_t *pNtk, int nLutSize, int fFixed, int fNewInterface)
Definition ioWriteVerilog.c:859
Io_WriteLutModule
void Io_WriteLutModule(FILE *pFile, int nLutSize)
Definition ioWriteVerilog.c:737
Io_WriteFixedModules
void Io_WriteFixedModules(FILE *pFile)
Definition ioWriteVerilog.c:743
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◆ Io_WriteVerilogLutInt()

void Io_WriteVerilogLutInt ( FILE * pFile,
Abc_Ntk_t * pNtk,
int nLutSize,
int fFixed,
int fNewInterface )

Definition at line 859 of file ioWriteVerilog.c.

860{
861 // write inputs and outputs
862// fprintf( pFile, "module %s ( gclk,\n ", Abc_NtkName(pNtk) );
863 fprintf( pFile, "module %s ( ", Io_WriteVerilogGetName(Abc_NtkName(pNtk)) );
864 // add the clock signal if it does not exist
865 if ( Abc_NtkLatchNum(pNtk) > 0 && Nm_ManFindIdByName(pNtk->pManName, "clock", ABC_OBJ_PI) == -1 )
866 fprintf( pFile, "clock, " );
867 // write other primary inputs
868 fprintf( pFile, "\n " );
869 if ( Abc_NtkPiNum(pNtk) > 0 )
870 {
871 Io_WriteVerilogPis( pFile, pNtk, 3 );
872 fprintf( pFile, ",\n " );
873 }
874 if ( Abc_NtkPoNum(pNtk) > 0 )
875 Io_WriteVerilogPos( pFile, pNtk, 3, fNewInterface );
876 fprintf( pFile, " );\n\n" );
877 // add the clock signal if it does not exist
878 if ( Abc_NtkLatchNum(pNtk) > 0 && Nm_ManFindIdByName(pNtk->pManName, "clock", ABC_OBJ_PI) == -1 )
879 fprintf( pFile, " input clock;\n" );
880 // write inputs, outputs, registers, and wires
881 if ( Abc_NtkPiNum(pNtk) > 0 )
882 {
883// fprintf( pFile, " input gclk," );
884 fprintf( pFile, " input " );
885 Io_WriteVerilogPis( pFile, pNtk, 10 );
886 fprintf( pFile, ";\n" );
887 }
888 if ( Abc_NtkPoNum(pNtk) > 0 )
889 {
890 fprintf( pFile, " output" );
891 Io_WriteVerilogPos( pFile, pNtk, 5, fNewInterface );
892 fprintf( pFile, ";\n\n" );
893 }
894 // if this is not a blackbox, write internal signals
895 if ( !Abc_NtkHasBlackbox(pNtk) )
896 {
897 if ( Abc_NtkLatchNum(pNtk) > 0 )
898 {
899 fprintf( pFile, " reg" );
900 Io_WriteVerilogRegs( pFile, pNtk, 4 );
901 fprintf( pFile, ";\n\n" );
902 }
903 if ( Io_WriteVerilogWiresCount(pNtk) > 0 )
904 {
905 fprintf( pFile, " wire" );
906 Io_WriteVerilogWires( pFile, pNtk, 4 );
907 fprintf( pFile, ";\n\n" );
908 }
909 // write nodes
910 Io_WriteVerilogObjectsLut( pFile, pNtk, nLutSize, fFixed );
911 // write registers
912 if ( Abc_NtkLatchNum(pNtk) > 0 )
913 {
914 fprintf( pFile, "\n" );
915 Io_WriteVerilogLatches( pFile, pNtk );
916 }
917 }
918 if ( fNewInterface )
919 Io_WriteVerilogAssigns( pFile, pNtk );
920 // finalize the file
921 fprintf( pFile, "\nendmodule\n\n" );
922}
ABC_OBJ_PI
@ ABC_OBJ_PI
Definition abc.h:89
Io_WriteVerilogObjectsLut
void Io_WriteVerilogObjectsLut(FILE *pFile, Abc_Ntk_t *pNtk, int nLutSize, int fFixed)
Definition ioWriteVerilog.c:775
Nm_ManFindIdByName
int Nm_ManFindIdByName(Nm_Man_t *p, char *pName, int Type)
Definition nmApi.c:219
Abc_Ntk_t_::pManName
Nm_Man_t * pManName
Definition abc.h:160
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◆ Io_WriteVerilogObjectsLut()

void Io_WriteVerilogObjectsLut ( FILE * pFile,
Abc_Ntk_t * pNtk,
int nLutSize,
int fFixed )

Definition at line 775 of file ioWriteVerilog.c.

776{
777 Abc_Ntk_t * pNtkBox;
778 Abc_Obj_t * pObj, * pTerm;
779 int i, k, Counter, nDigits, Length = 0;
780
781 // write boxes
782 nDigits = Abc_Base10Log( Abc_NtkBoxNum(pNtk)-Abc_NtkLatchNum(pNtk) );
783 Counter = 0;
784 Abc_NtkForEachBox( pNtk, pObj, i )
785 {
786 if ( Abc_ObjIsLatch(pObj) )
787 continue;
788 pNtkBox = (Abc_Ntk_t *)pObj->pData;
789 fprintf( pFile, " %s box%0*d", pNtkBox->pName, nDigits, Counter++ );
790 fprintf( pFile, "(" );
791 Abc_NtkForEachPi( pNtkBox, pTerm, k )
792 {
793 fprintf( pFile, ".%s", Io_WriteVerilogGetName(Abc_ObjName(Abc_ObjFanout0(pTerm))) );
794 fprintf( pFile, "(%s), ", Io_WriteVerilogGetName(Abc_ObjName(Abc_ObjFanin0(Abc_ObjFanin(pObj,k)))) );
795 }
796 Abc_NtkForEachPo( pNtkBox, pTerm, k )
797 {
798 fprintf( pFile, ".%s", Io_WriteVerilogGetName(Abc_ObjName(Abc_ObjFanin0(pTerm))) );
799 fprintf( pFile, "(%s)%s", Io_WriteVerilogGetName(Abc_ObjName(Abc_ObjFanout0(Abc_ObjFanout(pObj,k)))), k==Abc_NtkPoNum(pNtkBox)-1? "":", " );
800 }
801 fprintf( pFile, ");\n" );
802 }
803
804 // find the longest signal name
805 Abc_NtkForEachNode( pNtk, pObj, i )
806 {
807 Length = Abc_MaxInt( Length, strlen(Io_WriteVerilogGetName(Abc_ObjName(Abc_ObjFanout0(pObj)))) );
808 Abc_ObjForEachFanin( pObj, pTerm, k )
809 Length = Abc_MaxInt( Length, strlen(Io_WriteVerilogGetName(Abc_ObjName(pTerm))) );
810 }
811
812 // write LUT instances
813 nDigits = Abc_Base10Log( Abc_NtkNodeNum(pNtk) );
814 Counter = 0;
815 if ( fFixed )
816 Abc_NtkForEachNode( pNtk, pObj, i )
817 {
818 if ( pObj->fPersist )
819 {
820 int One = Abc_ObjFanin0(Abc_ObjFanin(pObj, 1))->fPersist && Abc_ObjFanin0(Abc_ObjFanin(pObj, 2))->fPersist;
821 fprintf( pFile, " MUXF%d ", 7+One );
822 fprintf( pFile, " mux_%0*d (", nDigits, Counter++ );
823 fprintf( pFile, " %*s", Length, Io_WriteVerilogGetName(Abc_ObjName(Abc_ObjFanout0(pObj))) );
824 for ( k = Abc_ObjFaninNum(pObj) - 1; k >= 0; k-- )
825 fprintf( pFile, ", %*s", Length, Io_WriteVerilogGetName(Abc_ObjName(Abc_ObjFanin(pObj, k))) );
826 fprintf( pFile, " );\n" );
827 }
828 else
829 {
830 word Truth = Abc_SopToTruth( (char *)pObj->pData, Abc_ObjFaninNum(pObj) );
831 fprintf( pFile, " LUT6 #(64\'h" );
832 fprintf( pFile, "%08x%08x", (unsigned)(Truth >> 32), (unsigned)Truth );
833 fprintf( pFile, ") lut_%0*d (", nDigits, Counter++ );
834 fprintf( pFile, " %*s", Length, Io_WriteVerilogGetName(Abc_ObjName(Abc_ObjFanout0(pObj))) );
835 for ( k = 0; k < Abc_ObjFaninNum(pObj); k++ )
836 fprintf( pFile, ", %*s", Length, Io_WriteVerilogGetName(Abc_ObjName(Abc_ObjFanin(pObj, k))) );
837 for ( ; k < 6; k++ )
838 fprintf( pFile, ", %*s", Length, "1\'b0" );
839 fprintf( pFile, " );\n" );
840 }
841 }
842 else
843 Abc_NtkForEachNode( pNtk, pObj, i )
844 {
845 word Truth = Abc_SopToTruth( (char *)pObj->pData, Abc_ObjFaninNum(pObj) );
846 fprintf( pFile, " lut%d #(%d\'h", nLutSize, 1<<nLutSize );
847 if ( nLutSize == 6 )
848 fprintf( pFile, "%08x%08x", (unsigned)(Truth >> 32), (unsigned)Truth );
849 else
850 fprintf( pFile, "%0*x", 1<<(nLutSize-2), Abc_InfoMask(1 << nLutSize) & (unsigned)Truth );
851 fprintf( pFile, ") lut_%0*d ( {", nDigits, Counter++ );
852 for ( k = nLutSize - 1; k >= Abc_ObjFaninNum(pObj); k-- )
853 fprintf( pFile, "%*s, ", Length, "1\'b0" );
854 for ( k = Abc_ObjFaninNum(pObj) - 1; k >= 0; k-- )
855 fprintf( pFile, "%*s%s", Length, Io_WriteVerilogGetName(Abc_ObjName(Abc_ObjFanin(pObj, k))), k==0 ? "":", " );
856 fprintf( pFile, "}, %*s );\n", Length, Io_WriteVerilogGetName(Abc_ObjName(Abc_ObjFanout0(pObj))) );
857 }
858}
Abc_NtkForEachPo
#define Abc_NtkForEachPo(pNtk, pPo, i)
Definition abc.h:520
Abc_ObjForEachFanin
#define Abc_ObjForEachFanin(pObj, pFanin, i)
Definition abc.h:527
Abc_NtkForEachPi
#define Abc_NtkForEachPi(pNtk, pPi, i)
Definition abc.h:516
Abc_SopToTruth
ABC_DLL word Abc_SopToTruth(char *pSop, int nInputs)
Definition abcSop.c:1314
Abc_NtkForEachBox
#define Abc_NtkForEachBox(pNtk, pObj, i)
Definition abc.h:498
word
unsigned __int64 word
DECLARATIONS ///.
Definition kitPerm.c:36
Abc_Obj_t_::pData
void * pData
Definition abc.h:145
Abc_Obj_t_::fPersist
unsigned fPersist
Definition abc.h:139
strlen
int strlen()
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