ABC: A System for Sequential Synthesis and Verification
 
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sswUnique.c File Reference
#include "sswInt.h"
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Functions

ABC_NAMESPACE_IMPL_START void Ssw_UniqueRegisterPairInfo (Ssw_Man_t *p)
 DECLARATIONS ///.
 
int Ssw_ManUniqueOne (Ssw_Man_t *p, Aig_Obj_t *pRepr, Aig_Obj_t *pObj, int fVerbose)
 
int Ssw_ManUniqueAddConstraint (Ssw_Man_t *p, Vec_Ptr_t *vCommon, int f1, int f2)
 

Function Documentation

◆ Ssw_ManUniqueAddConstraint()

int Ssw_ManUniqueAddConstraint ( Ssw_Man_t * p,
Vec_Ptr_t * vCommon,
int f1,
int f2 )

Function*************************************************************

Synopsis [Returns the output of the uniqueness constraint.]

Description []

SideEffects []

SeeAlso []

Definition at line 151 of file sswUnique.c.

152{
153 Aig_Obj_t * pObj, * pObj1New, * pObj2New, * pMiter, * pTotal;
154 int i, pLits[2];
155// int RetValue;
156 assert( Vec_PtrSize(vCommon) > 0 );
157 // generate the constraint
158 pTotal = Aig_ManConst0(p->pFrames);
159 Vec_PtrForEachEntry( Aig_Obj_t *, vCommon, pObj, i )
160 {
161 assert( Saig_ObjIsLo(p->pAig, pObj) );
162 pObj1New = Ssw_ObjFrame( p, pObj, f1 );
163 pObj2New = Ssw_ObjFrame( p, pObj, f2 );
164 pMiter = Aig_Exor( p->pFrames, pObj1New, pObj2New );
165 pTotal = Aig_Or( p->pFrames, pTotal, pMiter );
166 }
167 if ( Aig_ObjIsConst1(Aig_Regular(pTotal)) )
168 {
169// Abc_Print( 1, "Skipped\n" );
170 return 0;
171 }
172 // create CNF
173 Ssw_CnfNodeAddToSolver( p->pMSat, Aig_Regular(pTotal) );
174 // add output constraint
175 pLits[0] = toLitCond( Ssw_ObjSatNum(p->pMSat,Aig_Regular(pTotal)), Aig_IsComplement(pTotal) );
176/*
177 RetValue = sat_solver_addclause( p->pSat, pLits, pLits + 1 );
178 assert( RetValue );
179 // simplify the solver
180 if ( p->pSat->qtail != p->pSat->qhead )
181 {
182 RetValue = sat_solver_simplify(p->pSat);
183 assert( RetValue != 0 );
184 }
185*/
186 assert( p->iOutputLit == -1 );
187 p->iOutputLit = pLits[0];
188 return 1;
189}
struct Aig_Obj_t_ Aig_Obj_t
Definition aig.h:51
Aig_Obj_t * Aig_Exor(Aig_Man_t *p, Aig_Obj_t *p0, Aig_Obj_t *p1)
Definition aigOper.c:220
Aig_Obj_t * Aig_Or(Aig_Man_t *p, Aig_Obj_t *p0, Aig_Obj_t *p1)
Definition aigOper.c:259
Cube * p
Definition exorList.c:222
void Ssw_CnfNodeAddToSolver(Ssw_Sat_t *p, Aig_Obj_t *pObj)
Definition sswCnf.c:351
#define assert(ex)
Definition util_old.h:213
#define Vec_PtrForEachEntry(Type, vVec, pEntry, i)
MACRO DEFINITIONS ///.
Definition vecPtr.h:55
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◆ Ssw_ManUniqueOne()

int Ssw_ManUniqueOne ( Ssw_Man_t * p,
Aig_Obj_t * pRepr,
Aig_Obj_t * pObj,
int fVerbose )

Function*************************************************************

Synopsis [Returns 1 if uniqueness constraints can be added.]

Description []

SideEffects []

SeeAlso []

Definition at line 90 of file sswUnique.c.

91{
92 Aig_Obj_t * ppObjs[2], * pTemp;
93 int i, k, Value0, Value1, RetValue, fFeasible;
94
95 assert( p->pPars->nFramesK > 1 );
96 assert( p->vDiffPairs && Vec_IntSize(p->vDiffPairs) == Saig_ManRegNum(p->pAig) );
97
98 // compute the first support in terms of LOs
99 ppObjs[0] = pRepr;
100 ppObjs[1] = pObj;
101 Aig_SupportNodes( p->pAig, ppObjs, 2, p->vCommon );
102 // keep only LOs
103 RetValue = Vec_PtrSize( p->vCommon );
104 fFeasible = 0;
105 k = 0;
106 Vec_PtrForEachEntry( Aig_Obj_t *, p->vCommon, pTemp, i )
107 {
108 assert( Aig_ObjIsCi(pTemp) );
109 if ( !Saig_ObjIsLo(p->pAig, pTemp) )
110 continue;
111 assert( Aig_ObjCioId(pTemp) > 0 );
112 Vec_PtrWriteEntry( p->vCommon, k++, pTemp );
113 if ( Vec_IntEntry(p->vDiffPairs, Aig_ObjCioId(pTemp) - Saig_ManPiNum(p->pAig)) )
114 fFeasible = 1;
115 }
116 Vec_PtrShrink( p->vCommon, k );
117
118 if ( fVerbose )
119 Abc_Print( 1, "Node = %5d : Supp = %3d. Regs = %3d. Feasible = %s. ",
120 Aig_ObjId(pObj), RetValue, Vec_PtrSize(p->vCommon),
121 fFeasible? "yes": "no " );
122
123 // check the current values
124 RetValue = 1;
125 Vec_PtrForEachEntry( Aig_Obj_t *, p->vCommon, pTemp, i )
126 {
127 Value0 = Ssw_ManGetSatVarValue( p, pTemp, 0 );
128 Value1 = Ssw_ManGetSatVarValue( p, pTemp, 1 );
129 if ( Value0 != Value1 )
130 RetValue = 0;
131 if ( fVerbose )
132 Abc_Print( 1, "%d", Value0 ^ Value1 );
133 }
134 if ( fVerbose )
135 Abc_Print( 1, "\n" );
136
137 return RetValue && fFeasible;
138}
void Aig_SupportNodes(Aig_Man_t *p, Aig_Obj_t **ppObjs, int nObjs, Vec_Ptr_t *vSupp)
Definition aigDfs.c:868
int Ssw_ManGetSatVarValue(Ssw_Man_t *p, Aig_Obj_t *pObj, int f)
DECLARATIONS ///.
Definition sswSweep.c:46
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◆ Ssw_UniqueRegisterPairInfo()

ABC_NAMESPACE_IMPL_START void Ssw_UniqueRegisterPairInfo ( Ssw_Man_t * p)

DECLARATIONS ///.

CFile****************************************************************

FileName [sswSat.c]

SystemName [ABC: Logic synthesis and verification system.]

PackageName [Inductive prover with constraints.]

Synopsis [On-demand uniqueness constraints.]

Author [Alan Mishchenko]

Affiliation [UC Berkeley]

Date [Ver. 1.0. Started - September 1, 2008.]

Revision [

Id
sswSat.c,v 1.00 2008/09/01 00:00:00 alanmi Exp

] FUNCTION DEFINITIONS /// Function*************************************************************

Synopsis [Performs computation of signal correspondence with constraints.]

Description []

SideEffects []

SeeAlso []

Definition at line 45 of file sswUnique.c.

46{
47 Aig_Obj_t * pObjLo, * pObj0, * pObj1;
48 int i, RetValue, Counter;
49 if ( p->vDiffPairs == NULL )
50 p->vDiffPairs = Vec_IntAlloc( Saig_ManRegNum(p->pAig) );
51 Vec_IntClear( p->vDiffPairs );
52 Saig_ManForEachLo( p->pAig, pObjLo, i )
53 {
54 pObj0 = Ssw_ObjFrame( p, pObjLo, 0 );
55 pObj1 = Ssw_ObjFrame( p, pObjLo, 1 );
56 if ( pObj0 == pObj1 )
57 Vec_IntPush( p->vDiffPairs, 0 );
58 else if ( pObj0 == Aig_Not(pObj1) )
59 Vec_IntPush( p->vDiffPairs, 1 );
60// else
61// Vec_IntPush( p->vDiffPairs, 1 );
62 else if ( Aig_ObjPhaseReal(pObj0) != Aig_ObjPhaseReal(pObj1) )
63 Vec_IntPush( p->vDiffPairs, 1 );
64 else
65 {
66 RetValue = Ssw_NodesAreEquiv( p, Aig_Regular(pObj0), Aig_Regular(pObj1) );
67 Vec_IntPush( p->vDiffPairs, RetValue!=1 );
68 }
69 }
70 assert( Vec_IntSize(p->vDiffPairs) == Saig_ManRegNum(p->pAig) );
71 // count the number of ones
72 Counter = 0;
73 Vec_IntForEachEntry( p->vDiffPairs, RetValue, i )
74 Counter += RetValue;
75// Abc_Print( 1, "The number of different register pairs = %d.\n", Counter );
76}
#define Saig_ManForEachLo(p, pObj, i)
Definition saig.h:96
int Ssw_NodesAreEquiv(Ssw_Man_t *p, Aig_Obj_t *pOld, Aig_Obj_t *pNew)
DECLARATIONS ///.
Definition sswSat.c:45
#define Vec_IntForEachEntry(vVec, Entry, i)
MACRO DEFINITIONS ///.
Definition vecInt.h:54
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