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Classes | |
| struct | Acec_ParCec_t_ |
Typedefs | |
| typedef typedefABC_NAMESPACE_HEADER_START struct Acec_ParCec_t_ | Acec_ParCec_t |
| INCLUDES ///. | |
Functions | |
| Gia_Man_t * | Acec_ManDecla (Gia_Man_t *pGia, int fBooth, int fVerbose) |
| MACRO DEFINITIONS ///. | |
| void | Acec_ManCecSetDefaultParams (Acec_ParCec_t *p) |
| FUNCTION DEFINITIONS ///. | |
| int | Acec_Solve (Gia_Man_t *pGia0, Gia_Man_t *pGia1, Acec_ParCec_t *pPars) |
| Vec_Int_t * | Gia_ManDetectFullAdders (Gia_Man_t *p, int fVerbose, Vec_Int_t **vCutsXor2) |
| Vec_Int_t * | Gia_ManDetectHalfAdders (Gia_Man_t *p, int fVerbose) |
| FUNCTION DEFINITIONS ///. | |
| Vec_Int_t * | Gia_PolynReorder (Gia_Man_t *pGia, int fVerbose, int fVeryVerbose) |
| Vec_Int_t * | Gia_PolynFindOrder (Gia_Man_t *pGia, Vec_Int_t *vFadds, Vec_Int_t *vHadds, int fVerbose, int fVeryVerbose) |
| DECLARATIONS ///. | |
| void | Gia_PolynBuild (Gia_Man_t *pGia, Vec_Int_t *vOrder, int fSigned, int fVerbose, int fVeryVerbose) |
| Vec_Int_t * | Ree_ManComputeCuts (Gia_Man_t *p, Vec_Int_t **pvXors, int fVerbose) |
| int | Ree_ManCountFadds (Vec_Int_t *vAdds) |
| void | Ree_ManPrintAdders (Vec_Int_t *vAdds, int fVerbose) |
| Gia_Man_t * | Acec_Normalize (Gia_Man_t *pGia, int fBooth, int fVerbose) |
| typedef typedefABC_NAMESPACE_HEADER_START struct Acec_ParCec_t_ Acec_ParCec_t |
INCLUDES ///.
CFile****************************************************************
FileName [acec.h]
SystemName [ABC: Logic synthesis and verification system.]
PackageName [CEC for arithmetic circuits.]
Synopsis [External declarations.]
Author [Alan Mishchenko]
Affiliation [UC Berkeley]
Date [Ver. 1.0. Started - June 20, 2005.]
Revision [
] PARAMETERS /// BASIC TYPES ///
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extern |
FUNCTION DEFINITIONS ///.
Function*************************************************************
Synopsis [This procedure sets default parameters.]
Description []
SideEffects []
SeeAlso []
Definition at line 50 of file acecCore.c.

MACRO DEFINITIONS ///.
ITERATORS /// FUNCTION DECLARATIONS ///
Definition at line 418 of file acecCl.c.

Function*************************************************************
Synopsis []
Description []
SideEffects []
SeeAlso []
Definition at line 210 of file acecNorm.c.

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extern |
Function*************************************************************
Synopsis []
Description []
SideEffects []
SeeAlso []
Definition at line 488 of file acecCore.c.

Definition at line 442 of file acecFadds.c.


FUNCTION DEFINITIONS ///.
Function*************************************************************
Synopsis [Detecting HADDs in the AIG.]
Description []
SideEffects []
SeeAlso []
Definition at line 50 of file acecFadds.c.


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extern |
Definition at line 340 of file acecPolyn.c.

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extern |
DECLARATIONS ///.
CFile****************************************************************
FileName [acecOrder.c]
SystemName [ABC: Logic synthesis and verification system.]
PackageName [CEC for arithmetic circuits.]
Synopsis [Node ordering.]
Author [Alan Mishchenko]
Affiliation [UC Berkeley]
Date [Ver. 1.0. Started - June 20, 2005.]
Revision [
] FUNCTION DEFINITIONS /// Function*************************************************************
Synopsis []
Description []
SideEffects []
SeeAlso []
Definition at line 45 of file acecOrder.c.


Function*************************************************************
Synopsis []
Description []
SideEffects []
SeeAlso []
Definition at line 199 of file acecOrder.c.

Definition at line 408 of file acecRe.c.


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extern |
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extern |
Definition at line 564 of file acecRe.c.
