ABC: A System for Sequential Synthesis and Verification
 
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absOldRef.c
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1
20
21#include "abs.h"
22#include "proof/ssw/ssw.h"
23#include "proof/fra/fra.h"
24#include "bdd/bbr/bbr.h"
25#include "proof/pdr/pdr.h"
26#include "sat/bmc/bmc.h"
27
29
30
34
38
51{
52 memset( p, 0, sizeof(Gia_ParAbs_t) );
53 p->Algo = 0; // algorithm: CBA
54 p->nFramesMax = 10; // timeframes for PBA
55 p->nConfMax = 10000; // conflicts for PBA
56 p->fDynamic = 1; // dynamic unfolding for PBA
57 p->fConstr = 0; // use constraints
58 p->nFramesBmc = 250; // timeframes for BMC
59 p->nConfMaxBmc = 5000; // conflicts for BMC
60 p->nStableMax = 1000000; // the number of stable frames to quit
61 p->nRatio = 10; // ratio of flops to quit
62 p->nBobPar = 1000000; // the number of frames before trying to quit
63 p->fUseBdds = 0; // use BDDs to refine abstraction
64 p->fUseDprove = 0; // use 'dprove' to refine abstraction
65 p->fUseStart = 1; // use starting frame
66 p->fVerbose = 0; // verbose output
67 p->fVeryVerbose= 0; // printing additional information
68 p->Status = -1; // the problem status
69 p->nFramesDone = -1; // the number of rames covered
70}
71
72
85{
86 Abc_Cex_t * pCex;
87 Aig_Obj_t * pObj;
88 int i, f;
89 if ( !Saig_ManVerifyCex( pAbs, pCexAbs ) )
90 printf( "Saig_ManCexRemap(): The initial counter-example is invalid.\n" );
91// else
92// printf( "Saig_ManCexRemap(): The initial counter-example is correct.\n" );
93 // start the counter-example
94 pCex = Abc_CexAlloc( Aig_ManRegNum(p), Saig_ManPiNum(p), pCexAbs->iFrame+1 );
95 pCex->iFrame = pCexAbs->iFrame;
96 pCex->iPo = pCexAbs->iPo;
97 // copy the bit data
98 for ( f = 0; f <= pCexAbs->iFrame; f++ )
99 {
100 Saig_ManForEachPi( pAbs, pObj, i )
101 {
102 if ( i == Saig_ManPiNum(p) )
103 break;
104 if ( Abc_InfoHasBit( pCexAbs->pData, pCexAbs->nRegs + pCexAbs->nPis * f + i ) )
105 Abc_InfoSetBit( pCex->pData, pCex->nRegs + pCex->nPis * f + i );
106 }
107 }
108 // verify the counter example
109 if ( !Saig_ManVerifyCex( p, pCex ) )
110 {
111 printf( "Saig_ManCexRemap(): Counter-example is invalid.\n" );
112 Abc_CexFree( pCex );
113 pCex = NULL;
114 }
115 else
116 {
117 Abc_Print( 1, "Counter-example verification is successful.\n" );
118 Abc_Print( 1, "Output %d of miter \"%s\" was asserted in frame %d. \n", pCex->iPo, p->pName, pCex->iFrame );
119 }
120 return pCex;
121}
122
135{
136 Aig_Obj_t * pObj;
137 int i;
138 assert( pAbs->vCiNumsOrig != NULL );
139 Aig_ManForEachCi( p, pObj, i )
140 {
141 if ( Vec_IntEntry(pAbs->vCiNumsOrig, i) >= Saig_ManPiNum(p) )
142 return i;
143 }
144 return -1;
145}
146
158Aig_Man_t * Saig_ManCexRefine( Aig_Man_t * p, Aig_Man_t * pAbs, Vec_Int_t * vFlops, int nFrames, int nConfMaxOne, int fUseBdds, int fUseDprove, int fVerbose, int * pnUseStart, int * piRetValue, int * pnFrames )
159{
160 Vec_Int_t * vFlopsNew;
161 int i, Entry, RetValue;
162 *piRetValue = -1;
163 if ( fUseDprove && Aig_ManRegNum(pAbs) > 0 )
164 {
165/*
166 Fra_Sec_t SecPar, * pSecPar = &SecPar;
167 Fra_SecSetDefaultParams( pSecPar );
168 pSecPar->fVerbose = fVerbose;
169 RetValue = Fra_FraigSec( pAbs, pSecPar, NULL );
170*/
171 Aig_Man_t * pAbsOrpos = Saig_ManDupOrpos( pAbs );
172 Pdr_Par_t Pars, * pPars = &Pars;
174 pPars->nTimeOut = 10;
175 pPars->fVerbose = fVerbose;
176 if ( pPars->fVerbose )
177 printf( "Running property directed reachability...\n" );
178 RetValue = Pdr_ManSolve( pAbsOrpos, pPars );
179 if ( pAbsOrpos->pSeqModel )
180 pAbsOrpos->pSeqModel->iPo = Saig_ManFindFailedPoCex( pAbs, pAbsOrpos->pSeqModel );
181 pAbs->pSeqModel = pAbsOrpos->pSeqModel;
182 pAbsOrpos->pSeqModel = NULL;
183 Aig_ManStop( pAbsOrpos );
184 if ( RetValue )
185 *piRetValue = 1;
186
187 }
188 else if ( fUseBdds && (Aig_ManRegNum(pAbs) > 0 && Aig_ManRegNum(pAbs) <= 80) )
189 {
190 Saig_ParBbr_t Pars, * pPars = &Pars;
192 pPars->TimeLimit = 0;
193 pPars->nBddMax = 1000000;
194 pPars->nIterMax = nFrames;
195 pPars->fPartition = 1;
196 pPars->fReorder = 1;
197 pPars->fReorderImage = 1;
198 pPars->fVerbose = fVerbose;
199 pPars->fSilent = 0;
200 RetValue = Aig_ManVerifyUsingBdds( pAbs, pPars );
201 if ( RetValue )
202 *piRetValue = 1;
203 }
204 else
205 {
206 Saig_BmcPerform( pAbs, pnUseStart? *pnUseStart: 0, nFrames, 2000, 0, nConfMaxOne, 0, fVerbose, 0, pnFrames, 0, 0 );
207 }
208 if ( pAbs->pSeqModel == NULL )
209 return NULL;
210 if ( pnUseStart )
211 *pnUseStart = pAbs->pSeqModel->iFrame;
212// vFlopsNew = Saig_ManExtendCounterExampleTest( pAbs, Saig_ManCexFirstFlopPi(p, pAbs), pAbs->pSeqModel, 1, fVerbose );
213 vFlopsNew = Saig_ManExtendCounterExampleTest3( pAbs, Saig_ManCexFirstFlopPi(p, pAbs), pAbs->pSeqModel, fVerbose );
214 if ( vFlopsNew == NULL )
215 return NULL;
216 if ( Vec_IntSize(vFlopsNew) == 0 )
217 {
218 printf( "Discovered a true counter-example!\n" );
219 p->pSeqModel = Saig_ManCexRemap( p, pAbs, pAbs->pSeqModel );
220 Vec_IntFree( vFlopsNew );
221 *piRetValue = 0;
222 return NULL;
223 }
224 // vFlopsNew contains PI numbers that should be kept in pAbs
225 if ( fVerbose )
226 printf( "Adding %d registers to the abstraction (total = %d).\n\n", Vec_IntSize(vFlopsNew), Aig_ManRegNum(pAbs)+Vec_IntSize(vFlopsNew) );
227 // add to the abstraction
228 Vec_IntForEachEntry( vFlopsNew, Entry, i )
229 {
230 Entry = Vec_IntEntry(pAbs->vCiNumsOrig, Entry);
231 assert( Entry >= Saig_ManPiNum(p) );
232 assert( Entry < Aig_ManCiNum(p) );
233 Vec_IntPush( vFlops, Entry-Saig_ManPiNum(p) );
234 }
235 Vec_IntFree( vFlopsNew );
236
237 Vec_IntSort( vFlops, 0 );
238 Vec_IntForEachEntryStart( vFlops, Entry, i, 1 )
239 assert( Vec_IntEntry(vFlops, i-1) != Entry );
240
241 return Saig_ManDupAbstraction( p, vFlops );
242}
243
255int Saig_ManCexRefineStep( Aig_Man_t * p, Vec_Int_t * vFlops, Vec_Int_t * vFlopClasses, Abc_Cex_t * pCex, int nFfToAddMax, int fTryFour, int fSensePath, int fVerbose )
256{
257 Aig_Man_t * pAbs;
258 Vec_Int_t * vFlopsNew;
259 int i, Entry;
260 abctime clk = Abc_Clock();
261 pAbs = Saig_ManDupAbstraction( p, vFlops );
262 if ( fSensePath )
263 vFlopsNew = Saig_ManExtendCounterExampleTest2( pAbs, Saig_ManCexFirstFlopPi(p, pAbs), pCex, fVerbose );
264 else
265// vFlopsNew = Saig_ManExtendCounterExampleTest( pAbs, Saig_ManCexFirstFlopPi(p, pAbs), pCex, fTryFour, fVerbose );
266 vFlopsNew = Saig_ManExtendCounterExampleTest3( pAbs, Saig_ManCexFirstFlopPi(p, pAbs), pCex, fVerbose );
267 if ( vFlopsNew == NULL )
268 {
269 Aig_ManStop( pAbs );
270 return 0;
271 }
272 if ( Vec_IntSize(vFlopsNew) == 0 )
273 {
274 printf( "Refinement did not happen. Discovered a true counter-example.\n" );
275 printf( "Remapping counter-example from %d to %d primary inputs.\n", Aig_ManCiNum(pAbs), Aig_ManCiNum(p) );
276 p->pSeqModel = Saig_ManCexRemap( p, pAbs, pCex );
277 Vec_IntFree( vFlopsNew );
278 Aig_ManStop( pAbs );
279 return 0;
280 }
281 if ( fVerbose )
282 {
283 printf( "Adding %d registers to the abstraction (total = %d). ", Vec_IntSize(vFlopsNew), Aig_ManRegNum(p)+Vec_IntSize(vFlopsNew) );
284 Abc_PrintTime( 1, "Time", Abc_Clock() - clk );
285 }
286 // vFlopsNew contains PI numbers that should be kept in pAbs
287 // select the most useful flops among those to be added
288 if ( nFfToAddMax > 0 && Vec_IntSize(vFlopsNew) > nFfToAddMax )
289 {
290 Vec_Int_t * vFlopsNewBest;
291 // shift the indices
292 Vec_IntForEachEntry( vFlopsNew, Entry, i )
293 Vec_IntAddToEntry( vFlopsNew, i, -Saig_ManPiNum(p) );
294 // create new flops
295 vFlopsNewBest = Saig_ManCbaFilterFlops( p, pCex, vFlopClasses, vFlopsNew, nFfToAddMax );
296 assert( Vec_IntSize(vFlopsNewBest) == nFfToAddMax );
297 printf( "Filtering flops based on cost (%d -> %d).\n", Vec_IntSize(vFlopsNew), Vec_IntSize(vFlopsNewBest) );
298 // update
299 Vec_IntFree( vFlopsNew );
300 vFlopsNew = vFlopsNewBest;
301 // shift the indices
302 Vec_IntForEachEntry( vFlopsNew, Entry, i )
303 Vec_IntAddToEntry( vFlopsNew, i, Saig_ManPiNum(p) );
304 }
305 // add to the abstraction
306 Vec_IntForEachEntry( vFlopsNew, Entry, i )
307 {
308 Entry = Vec_IntEntry(pAbs->vCiNumsOrig, Entry);
309 assert( Entry >= Saig_ManPiNum(p) );
310 assert( Entry < Aig_ManCiNum(p) );
311 Vec_IntPush( vFlops, Entry-Saig_ManPiNum(p) );
312 }
313 Vec_IntFree( vFlopsNew );
314 Aig_ManStop( pAbs );
315 return 1;
316}
317
330{
331 Vec_Int_t * vFlops;
332 int i, Entry;
333 vFlops = Vec_IntAlloc( 100 );
334 Vec_IntForEachEntry( vFlopClasses, Entry, i )
335 if ( Entry )
336 Vec_IntPush( vFlops, i );
337 return vFlops;
338}
339
352{
353 Vec_Int_t * vFlopClasses;
354 int i, Entry;
355 vFlopClasses = Vec_IntStart( Gia_ManRegNum(pGia) );
356 Vec_IntForEachEntry( vFlops, Entry, i )
357 Vec_IntWriteEntry( vFlopClasses, Entry, 1 );
358 return vFlopClasses;
359}
360
372int Gia_ManCexAbstractionRefine( Gia_Man_t * pGia, Abc_Cex_t * pCex, int nFfToAddMax, int fTryFour, int fSensePath, int fVerbose )
373{
374 Aig_Man_t * pNew;
375 Vec_Int_t * vFlops;
376 if ( pGia->vFlopClasses == NULL )
377 {
378 printf( "Gia_ManCexAbstractionRefine(): Abstraction latch map is missing.\n" );
379 return -1;
380 }
381 pNew = Gia_ManToAig( pGia, 0 );
382 vFlops = Gia_ManClasses2Flops( pGia->vFlopClasses );
383 if ( !Saig_ManCexRefineStep( pNew, vFlops, pGia->vFlopClasses, pCex, nFfToAddMax, fTryFour, fSensePath, fVerbose ) )
384 {
385 pGia->pCexSeq = pNew->pSeqModel; pNew->pSeqModel = NULL;
386 Vec_IntFree( vFlops );
387 Aig_ManStop( pNew );
388 return 0;
389 }
390 Vec_IntFree( pGia->vFlopClasses );
391 pGia->vFlopClasses = Gia_ManFlops2Classes( pGia, vFlops );
392 Vec_IntFree( vFlops );
393 Aig_ManStop( pNew );
394 return -1;
395}
396
397
410{
411 int nUseStart = 0;
412 Aig_Man_t * pAbs, * pTemp;
413 Vec_Int_t * vFlops;
414 int Iter;//, clk = Abc_Clock(), clk2 = Abc_Clock();//, iFlop;
415 assert( Aig_ManRegNum(p) > 0 );
416 if ( pPars->fVerbose )
417 printf( "Performing counter-example-based refinement.\n" );
419 vFlops = Vec_IntStartNatural( 1 );
420/*
421 iFlop = Saig_ManFindFirstFlop( p );
422 assert( iFlop >= 0 );
423 vFlops = Vec_IntAlloc( 1 );
424 Vec_IntPush( vFlops, iFlop );
425*/
426 // create the resulting AIG
427 pAbs = Saig_ManDupAbstraction( p, vFlops );
428 if ( !pPars->fVerbose )
429 {
430 printf( "Init : " );
431 Aig_ManPrintStats( pAbs );
432 }
433 printf( "Refining abstraction...\n" );
434 for ( Iter = 0; ; Iter++ )
435 {
436 pTemp = Saig_ManCexRefine( p, pAbs, vFlops, pPars->nFramesBmc, pPars->nConfMaxBmc, pPars->fUseBdds, pPars->fUseDprove, pPars->fVerbose, pPars->fUseStart?&nUseStart:NULL, &pPars->Status, &pPars->nFramesDone );
437 if ( pTemp == NULL )
438 {
439 ABC_FREE( p->pSeqModel );
440 p->pSeqModel = pAbs->pSeqModel;
441 pAbs->pSeqModel = NULL;
442 Aig_ManStop( pAbs );
443 break;
444 }
445 Aig_ManStop( pAbs );
446 pAbs = pTemp;
447 printf( "ITER %4d : ", Iter );
448 if ( !pPars->fVerbose )
449 Aig_ManPrintStats( pAbs );
450 // output the intermediate result of abstraction
451 Ioa_WriteAiger( pAbs, "gabs.aig", 0, 0 );
452// printf( "Intermediate abstracted model was written into file \"%s\".\n", "gabs.aig" );
453 // check if the ratio is reached
454 if ( 100.0*(Aig_ManRegNum(p)-Aig_ManRegNum(pAbs))/Aig_ManRegNum(p) < 1.0*pPars->nRatio )
455 {
456 printf( "Refinements is stopped because flop reduction is less than %d%%\n", pPars->nRatio );
457 Aig_ManStop( pAbs );
458 pAbs = NULL;
459 Vec_IntFree( vFlops );
460 vFlops = NULL;
461 break;
462 }
463 }
464 return vFlops;
465}
466
467
471
472
474
ABC_INT64_T abctime
Definition abc_global.h:332
#define ABC_FREE(obj)
Definition abc_global.h:267
#define ABC_NAMESPACE_IMPL_START
#define ABC_NAMESPACE_IMPL_END
int Saig_ManCexFirstFlopPi(Aig_Man_t *p, Aig_Man_t *pAbs)
Definition absOldRef.c:134
Aig_Man_t * Saig_ManCexRefine(Aig_Man_t *p, Aig_Man_t *pAbs, Vec_Int_t *vFlops, int nFrames, int nConfMaxOne, int fUseBdds, int fUseDprove, int fVerbose, int *pnUseStart, int *piRetValue, int *pnFrames)
Definition absOldRef.c:158
int Gia_ManCexAbstractionRefine(Gia_Man_t *pGia, Abc_Cex_t *pCex, int nFfToAddMax, int fTryFour, int fSensePath, int fVerbose)
Definition absOldRef.c:372
ABC_NAMESPACE_IMPL_START void Gia_ManAbsSetDefaultParams(Gia_ParAbs_t *p)
DECLARATIONS ///.
Definition absOldRef.c:50
Vec_Int_t * Gia_ManClasses2Flops(Vec_Int_t *vFlopClasses)
Definition absOldRef.c:329
int Saig_ManCexRefineStep(Aig_Man_t *p, Vec_Int_t *vFlops, Vec_Int_t *vFlopClasses, Abc_Cex_t *pCex, int nFfToAddMax, int fTryFour, int fSensePath, int fVerbose)
Definition absOldRef.c:255
Vec_Int_t * Saig_ManCexAbstractionFlops(Aig_Man_t *p, Gia_ParAbs_t *pPars)
Definition absOldRef.c:409
Abc_Cex_t * Saig_ManCexRemap(Aig_Man_t *p, Aig_Man_t *pAbs, Abc_Cex_t *pCexAbs)
Definition absOldRef.c:84
Vec_Int_t * Gia_ManFlops2Classes(Gia_Man_t *pGia, Vec_Int_t *vFlops)
Definition absOldRef.c:351
struct Gia_ParAbs_t_ Gia_ParAbs_t
Definition abs.h:84
Vec_Int_t * Saig_ManExtendCounterExampleTest2(Aig_Man_t *p, int iFirstPi, Abc_Cex_t *pCex, int fVerbose)
Definition absOldSim.c:443
Vec_Int_t * Saig_ManCbaFilterFlops(Aig_Man_t *pAig, Abc_Cex_t *pAbsCex, Vec_Int_t *vFlopClasses, Vec_Int_t *vAbsFfsToAdd, int nFfsToSelect)
FUNCTION DEFINITIONS ///.
Definition absOldCex.c:66
void Aig_ManSetCioIds(Aig_Man_t *p)
Definition aigUtil.c:978
void Aig_ManStop(Aig_Man_t *p)
Definition aigMan.c:187
#define Aig_ManForEachCi(p, pObj, i)
ITERATORS ///.
Definition aig.h:393
struct Aig_Obj_t_ Aig_Obj_t
Definition aig.h:51
void Aig_ManPrintStats(Aig_Man_t *p)
Definition aigMan.c:379
typedefABC_NAMESPACE_HEADER_START struct Aig_Man_t_ Aig_Man_t
INCLUDES ///.
Definition aig.h:50
typedefABC_NAMESPACE_IMPL_START struct Vec_Int_t_ Vec_Int_t
DECLARATIONS ///.
Definition bblif.c:37
int Saig_BmcPerform(Aig_Man_t *pAig, int nStart, int nFramesMax, int nNodesMax, int nTimeOut, int nConfMaxOne, int nConfMaxAll, int fVerbose, int fVerbOverwrite, int *piFrames, int fSilent, int fUseSatoko)
Definition bmcBmc2.c:811
Cube * p
Definition exorList.c:222
Aig_Man_t * Gia_ManToAig(Gia_Man_t *p, int fChoices)
Definition giaAig.c:318
struct Gia_Man_t_ Gia_Man_t
Definition gia.h:96
void Ioa_WriteAiger(Aig_Man_t *pMan, char *pFileName, int fWriteSymbols, int fCompact)
void Pdr_ManSetDefaultParams(Pdr_Par_t *pPars)
MACRO DEFINITIONS ///.
Definition pdrCore.c:50
typedefABC_NAMESPACE_HEADER_START struct Pdr_Par_t_ Pdr_Par_t
INCLUDES ///.
Definition pdr.h:40
int Pdr_ManSolve(Aig_Man_t *p, Pdr_Par_t *pPars)
Definition pdrCore.c:1765
void Bbr_ManSetDefaultParams(Saig_ParBbr_t *p)
Definition saigDup.c:593
int Aig_ManVerifyUsingBdds(Aig_Man_t *pInit, Saig_ParBbr_t *pPars)
Definition saigDup.c:592
Vec_Int_t * Saig_ManExtendCounterExampleTest3(Aig_Man_t *pAig, int iFirstFlopPi, Abc_Cex_t *pCex, int fVerbose)
Definition saigRefSat.c:930
struct Saig_ParBbr_t_ Saig_ParBbr_t
Definition saig.h:53
Aig_Man_t * Saig_ManDupAbstraction(Aig_Man_t *pAig, Vec_Int_t *vFlops)
Definition saigDup.c:207
int Saig_ManFindFailedPoCex(Aig_Man_t *pAig, Abc_Cex_t *p)
Definition saigDup.c:436
Aig_Man_t * Saig_ManDupOrpos(Aig_Man_t *p)
DECLARATIONS ///.
Definition saigDup.c:45
#define Saig_ManForEachPi(p, pObj, i)
Definition saig.h:91
int Saig_ManVerifyCex(Aig_Man_t *pAig, Abc_Cex_t *p)
Definition saigDup.c:281
Abc_Cex_t * pCexSeq
Definition gia.h:150
Vec_Int_t * vFlopClasses
Definition gia.h:156
int nRatio
Definition abs.h:95
int Status
Definition abs.h:104
int fUseBdds
Definition abs.h:99
int nFramesBmc
Definition abs.h:92
int nFramesDone
Definition abs.h:105
int fUseStart
Definition abs.h:101
int fVerbose
Definition abs.h:102
int nConfMaxBmc
Definition abs.h:93
int fUseDprove
Definition abs.h:100
int nBddMax
Definition saig.h:57
int fReorder
Definition saig.h:60
int fPartition
Definition saig.h:59
int fSilent
Definition saig.h:63
int fReorderImage
Definition saig.h:61
int TimeLimit
Definition saig.h:56
int fVerbose
Definition saig.h:62
int nIterMax
Definition saig.h:58
void Abc_CexFree(Abc_Cex_t *p)
Definition utilCex.c:382
ABC_NAMESPACE_IMPL_START Abc_Cex_t * Abc_CexAlloc(int nRegs, int nRealPis, int nFrames)
DECLARATIONS ///.
Definition utilCex.c:51
typedefABC_NAMESPACE_HEADER_START struct Abc_Cex_t_ Abc_Cex_t
INCLUDES ///.
Definition utilCex.h:39
#define assert(ex)
Definition util_old.h:213
char * memset()
#define Vec_IntForEachEntry(vVec, Entry, i)
MACRO DEFINITIONS ///.
Definition vecInt.h:54
#define Vec_IntForEachEntryStart(vVec, Entry, i, Start)
Definition vecInt.h:56