ABC: A System for Sequential Synthesis and Verification
 
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cecSatG3.c
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1
20
21#include "aig/gia/gia.h"
22#include "misc/util/utilTruth.h"
23#include "cec.h"
24#include "aig/gia/giaCSatP.h"
25#include <stdlib.h>
26
27#define USE_GLUCOSE2
28
29#ifdef USE_GLUCOSE2
30
31#include "sat/glucose2/AbcGlucose2.h"
32
33#define sat_solver bmcg2_sat_solver
34#define sat_solver_start bmcg2_sat_solver_start
35#define sat_solver_stop bmcg2_sat_solver_stop
36#define sat_solver_addclause bmcg2_sat_solver_addclause
37#define sat_solver_add_and bmcg2_sat_solver_add_and
38#define sat_solver_add_xor bmcg2_sat_solver_add_xor
39#define sat_solver_addvar bmcg2_sat_solver_addvar
40#define sat_solver_read_cex_varvalue bmcg2_sat_solver_read_cex_varvalue
41#define sat_solver_reset bmcg2_sat_solver_reset
42#define sat_solver_set_conflict_budget bmcg2_sat_solver_set_conflict_budget
43#define sat_solver_conflictnum bmcg2_sat_solver_conflictnum
44#define sat_solver_solve bmcg2_sat_solver_solve
45#define sat_solver_read_cex_varvalue bmcg2_sat_solver_read_cex_varvalue
46#define sat_solver_read_cex bmcg2_sat_solver_read_cex
47#define sat_solver_jftr bmcg2_sat_solver_jftr
48#define sat_solver_set_jftr bmcg2_sat_solver_set_jftr
49#define sat_solver_set_var_fanin_lit bmcg2_sat_solver_set_var_fanin_lit
50#define sat_solver_start_new_round bmcg2_sat_solver_start_new_round
51#define sat_solver_mark_cone bmcg2_sat_solver_mark_cone
52
53#else
54
55#include "sat/glucose/AbcGlucose.h"
56
57#define sat_solver bmcg_sat_solver
58#define sat_solver_start bmcg_sat_solver_start
59#define sat_solver_stop bmcg_sat_solver_stop
60#define sat_solver_addclause bmcg_sat_solver_addclause
61#define sat_solver_add_and bmcg_sat_solver_add_and
62#define sat_solver_add_xor bmcg_sat_solver_add_xor
63#define sat_solver_addvar bmcg_sat_solver_addvar
64#define sat_solver_read_cex_varvalue bmcg_sat_solver_read_cex_varvalue
65#define sat_solver_reset bmcg_sat_solver_reset
66#define sat_solver_set_conflict_budget bmcg_sat_solver_set_conflict_budget
67#define sat_solver_conflictnum bmcg_sat_solver_conflictnum
68#define sat_solver_solve bmcg_sat_solver_solve
69#define sat_solver_read_cex_varvalue bmcg_sat_solver_read_cex_varvalue
70#define sat_solver_read_cex bmcg_sat_solver_read_cex
71#define sat_solver_jftr bmcg_sat_solver_jftr
72#define sat_solver_set_jftr bmcg_sat_solver_set_jftr
73#define sat_solver_set_var_fanin_lit bmcg_sat_solver_set_var_fanin_lit
74#define sat_solver_start_new_round bmcg_sat_solver_start_new_round
75#define sat_solver_mark_cone bmcg_sat_solver_mark_cone
76
77#endif
78
79ABC_NAMESPACE_IMPL_START
80
81
85
86// SAT solving manager
87typedef struct Cec5_Man_t_ Cec5_Man_t;
88struct Cec5_Man_t_
89{
90 Cec_ParFra_t * pPars; // parameters
91 Gia_Man_t * pAig; // user's AIG
92 Gia_Man_t * pNew; // internal AIG
93 // SAT solving
94 sat_solver * pSat; // SAT solver
95 Vec_Ptr_t * vFrontier; // CNF construction
96 Vec_Ptr_t * vFanins; // CNF construction
97 Vec_Int_t * vCexMin; // minimized CEX
98 Vec_Int_t * vClassUpdates; // updated equiv classes
99 Vec_Int_t * vCexStamps; // time stamps
100 Vec_Int_t * vCands;
101 Vec_Int_t * vVisit;
102 Vec_Int_t * vPat;
103 Vec_Int_t * vDisprPairs;
104 Vec_Bit_t * vFails;
105 Vec_Bit_t * vCoDrivers;
106 int iPosRead; // candidate reading position
107 int iPosWrite; // candidate writing position
108 int iLastConst; // last const node proved
109 // refinement
110 Vec_Int_t * vRefClasses;
111 Vec_Int_t * vRefNodes;
112 Vec_Int_t * vRefBins;
113 int * pTable;
114 int nTableSize;
115 // statistics
116 int nItersSim;
117 int nItersSat;
118 int nAndNodes;
119 int nPatterns;
120 int nSatSat;
121 int nSatUnsat;
122 int nSatUndec;
123 int nCallsSince;
124 int nSimulates;
125 int nRecycles;
126 int nConflicts[3][3];
127 int nGates[2];
128 int nFaster[2];
129 abctime timeCnf;
130 abctime timeGenPats;
131 abctime timeSatSat0;
132 abctime timeSatUnsat0;
133 abctime timeSatSat;
134 abctime timeSatUnsat;
135 abctime timeSatUndec;
136 abctime timeSim;
137 abctime timeRefine;
138 abctime timeResimGlo;
139 abctime timeResimLoc;
140 abctime timeStart;
141
142 int simTravId;
143 Vec_Int_t * vPiPatsCache;
144 int fEec;
145 int LocalBatchSize;
146 Vec_Bit_t * vCexSite;
147 int simBound;
148 int simStart;
149 int approxLim;
150 int simGlobalTop;
151 int simBatchFactor;
152 int adaRecycle;
153};
154
155static inline int Cec5_ObjSatId( Gia_Man_t * p, Gia_Obj_t * pObj ) { return Gia_ObjCopy2Array(p, Gia_ObjId(p, pObj)); }
156static inline int Cec5_ObjSetSatId( Gia_Man_t * p, Gia_Obj_t * pObj, int Num ) { assert(Cec5_ObjSatId(p, pObj) == -1); Gia_ObjSetCopy2Array(p, Gia_ObjId(p, pObj), Num); Vec_IntPush(&p->vSuppVars, Gia_ObjId(p, pObj)); if ( Gia_ObjIsCi(pObj) ) Vec_IntPushTwo(&p->vCopiesTwo, Gia_ObjId(p, pObj), Num); assert(Vec_IntSize(&p->vVarMap) == Num); Vec_IntPush(&p->vVarMap, Gia_ObjId(p, pObj)); return Num; }
157static inline void Cec5_ObjCleanSatId( Gia_Man_t * p, Gia_Obj_t * pObj ) { assert(Cec5_ObjSatId(p, pObj) != -1); Gia_ObjSetCopy2Array(p, Gia_ObjId(p, pObj), -1); }
158
162
174Vec_Wrd_t * Cec5_EvalCombine( Vec_Int_t * vPats, int nPats, int nInputs, int nWords )
175{
176 //Vec_Wrd_t * vSimsPi = Vec_WrdStart( nInputs * nWords );
177 Vec_Wrd_t * vSimsPi = Vec_WrdStartRandom( nInputs * nWords );
178 int i, k, iLit, iPat = 0; word * pSim;
179 for ( i = 0; i < Vec_IntSize(vPats); i += Vec_IntEntry(vPats, i), iPat++ )
180 for ( k = 1; k < Vec_IntEntry(vPats, i)-1; k++ )
181 if ( (iLit = Vec_IntEntry(vPats, i+k)) )
182 {
183 assert( Abc_Lit2Var(iLit) > 0 && Abc_Lit2Var(iLit) <= nInputs );
184 pSim = Vec_WrdEntryP( vSimsPi, (Abc_Lit2Var(iLit)-1)*nWords );
185 if ( Abc_InfoHasBit( (unsigned*)pSim, iPat ) != Abc_LitIsCompl(iLit) )
186 Abc_InfoXorBit( (unsigned*)pSim, iPat );
187 }
188 assert( iPat == nPats );
189 return vSimsPi;
190}
191void Cec5_EvalPatterns( Gia_Man_t * p, Vec_Int_t * vPats, int nPats )
192{
193 int nWords = Abc_Bit6WordNum(nPats);
194 Vec_Wrd_t * vSimsPi = Cec5_EvalCombine( vPats, nPats, Gia_ManCiNum(p), nWords );
195 Vec_Wrd_t * vSimsPo = Gia_ManSimPatSimOut( p, vSimsPi, 1 );
196 int i, Count = 0, nErrors = 0;
197 for ( i = 0; i < Gia_ManCoNum(p); i++ )
198 {
199 int CountThis = Abc_TtCountOnesVec( Vec_WrdEntryP(vSimsPo, i*nWords), nWords );
200 if ( CountThis == 0 )
201 continue;
202 printf( "%d ", CountThis );
203 nErrors += CountThis;
204 Count++;
205 }
206 printf( "\nDetected %d error POs with %d errors (average %.2f).\n", Count, nErrors, 1.0*nErrors/Abc_MaxInt(1, Count) );
207 Vec_WrdFree( vSimsPi );
208 Vec_WrdFree( vSimsPo );
209}
210
222void Cec5_ManSetParams( Cec_ParFra_t * pPars )
223{
224 memset( pPars, 0, sizeof(Cec_ParFra_t) );
225 pPars->jType = 2; // solver type
226 pPars->fSatSweeping = 1; // conflict limit at a node
227 pPars->nWords = 4; // simulation words
228 pPars->nRounds = 10; // simulation rounds
229 pPars->nItersMax = 2000; // this is a miter
230 pPars->nBTLimit = 1000000; // use logic cones
231 pPars->nBTLimitPo = 0; // use logic outputs
232 pPars->nSatVarMax = 1000; // the max number of SAT variables before recycling SAT solver
233 pPars->nCallsRecycle = 500; // calls to perform before recycling SAT solver
234 pPars->nGenIters = 100; // pattern generation iterations
235}
236
248Cec5_Man_t * Cec5_ManCreate( Gia_Man_t * pAig, Cec_ParFra_t * pPars )
249{
250 Cec5_Man_t * p = ABC_CALLOC( Cec5_Man_t, 1 );
251 memset( p, 0, sizeof(Cec5_Man_t) );
252 p->timeStart = Abc_Clock();
253 p->pPars = pPars;
254 p->pAig = pAig;
255 p->pSat = sat_solver_start();
256 sat_solver_set_jftr( p->pSat, pPars->jType );
257 p->vFrontier = Vec_PtrAlloc( 1000 );
258 p->vFanins = Vec_PtrAlloc( 100 );
259 p->vCexMin = Vec_IntAlloc( 100 );
260 p->vClassUpdates = Vec_IntAlloc( 100 );
261 p->vCexStamps = Vec_IntStart( Gia_ManObjNum(pAig) );
262 p->vCands = Vec_IntAlloc( 100 );
263 p->vVisit = Vec_IntAlloc( 100 );
264 p->vPat = Vec_IntAlloc( 100 );
265 p->vDisprPairs = Vec_IntAlloc( 100 );
266 p->vFails = Vec_BitStart( Gia_ManObjNum(pAig) );
267 //pAig->pData = p->pSat; // point AIG manager to the solver
268 //Vec_IntFreeP( &p->pAig->vPats );
269 //p->pAig->vPats = Vec_IntAlloc( 1000 );
270 p->simTravId = 0;
271 p->vPiPatsCache = Vec_IntAlloc( 100 );
272 p->fEec = 0;
273 p->LocalBatchSize= 8;
274 p->vCexSite = Vec_BitStart( Gia_ManObjNum(pAig) );
275 Vec_BitFill( p->vCexSite, Gia_ManObjNum(pAig), 0 );
276 p->simBound = pPars->nWords;
277 p->simStart = 0;
278 p->approxLim = 600;
279 p->simBatchFactor= 1;
280 p->simGlobalTop = 0;
281 p->adaRecycle = 500;
282 if ( pPars->nBTLimitPo )
283 {
284 int i, Driver;
285 p->vCoDrivers = Vec_BitStart( Gia_ManObjNum(pAig) );
286 Gia_ManForEachCoDriverId( pAig, Driver, i )
287 Vec_BitWriteEntry( p->vCoDrivers, Driver, 1 );
288 }
289 return p;
290}
291void Cec5_ManDestroy( Cec5_Man_t * p )
292{
293 if ( p->pPars->fVerbose )
294 {
295 abctime timeTotal = Abc_Clock() - p->timeStart;
296 abctime timeSat = p->timeSatSat0 + p->timeSatSat + p->timeSatUnsat0 + p->timeSatUnsat + p->timeSatUndec;
297 abctime timeOther = timeTotal - timeSat - p->timeSim - p->timeRefine - p->timeResimLoc - p->timeGenPats;// - p->timeResimGlo;
298 ABC_PRTP( "SAT solving ", timeSat, timeTotal );
299 ABC_PRTP( " sat(easy) ", p->timeSatSat0, timeTotal );
300 ABC_PRTP( " sat ", p->timeSatSat, timeTotal );
301 ABC_PRTP( " unsat(easy)", p->timeSatUnsat0, timeTotal );
302 ABC_PRTP( " unsat ", p->timeSatUnsat, timeTotal );
303 ABC_PRTP( " fail ", p->timeSatUndec, timeTotal );
304 ABC_PRTP( "Generate CNF ", p->timeCnf, timeTotal );
305 ABC_PRTP( "Generate pats", p->timeGenPats, timeTotal );
306 ABC_PRTP( "Simulation ", p->timeSim, timeTotal );
307 ABC_PRTP( "Refinement ", p->timeRefine, timeTotal );
308 ABC_PRTP( "Resim global ", p->timeResimGlo, timeTotal );
309 ABC_PRTP( "Resim local ", p->timeResimLoc, timeTotal );
310 ABC_PRTP( "Other ", timeOther, timeTotal );
311 ABC_PRTP( "TOTAL ", timeTotal, timeTotal );
312 fflush( stdout );
313 }
314 //printf( "Recorded %d patterns with %d literals (average %.2f).\n",
315 // p->pAig->nBitPats, Vec_IntSize(p->pAig->vPats) - 2*p->pAig->nBitPats, 1.0*Vec_IntSize(p->pAig->vPats)/Abc_MaxInt(1, p->pAig->nBitPats)-2 );
316 //Cec5_EvalPatterns( p->pAig, p->pAig->vPats, p->pAig->nBitPats );
317 //Vec_IntFreeP( &p->pAig->vPats );
318 Vec_WrdFreeP( &p->pAig->vSims );
319 Vec_WrdFreeP( &p->pAig->vSimsPi );
320 Gia_ManCleanMark01( p->pAig );
321 sat_solver_stop( p->pSat );
322 Gia_ManStopP( &p->pNew );
323 Vec_PtrFreeP( &p->vFrontier );
324 Vec_PtrFreeP( &p->vFanins );
325 Vec_IntFreeP( &p->vCexMin );
326 Vec_IntFreeP( &p->vClassUpdates );
327 Vec_IntFreeP( &p->vCexStamps );
328 Vec_IntFreeP( &p->vCands );
329 Vec_IntFreeP( &p->vVisit );
330 Vec_IntFreeP( &p->vPat );
331 Vec_IntFreeP( &p->vDisprPairs );
332 Vec_BitFreeP( &p->vFails );
333 Vec_BitFreeP( &p->vCoDrivers );
334 Vec_IntFreeP( &p->vRefClasses );
335 Vec_IntFreeP( &p->vRefNodes );
336 Vec_IntFreeP( &p->vRefBins );
337 Vec_IntFreeP( &p->vPiPatsCache );
338 Vec_BitFreeP( &p->vCexSite );
339 ABC_FREE( p->pTable );
340 ABC_FREE( p );
341}
342Gia_Man_t * Cec5_ManStartNew( Gia_Man_t * pAig )
343{
344 Gia_Obj_t * pObj; int i;
345 Gia_Man_t * pNew = Gia_ManStart( Gia_ManObjNum(pAig) );
346 pNew->pName = Abc_UtilStrsav( pAig->pName );
347 pNew->pSpec = Abc_UtilStrsav( pAig->pSpec );
348 if ( pAig->pMuxes )
349 pNew->pMuxes = ABC_CALLOC( unsigned, pNew->nObjsAlloc );
350 Gia_ManFillValue( pAig );
351 Gia_ManConst0(pAig)->Value = 0;
352 Gia_ManForEachCi( pAig, pObj, i )
353 pObj->Value = Gia_ManAppendCi( pNew );
354 Gia_ManHashAlloc( pNew );
355 Vec_IntFill( &pNew->vCopies2, Gia_ManObjNum(pAig), -1 );
356 Gia_ManSetRegNum( pNew, Gia_ManRegNum(pAig) );
357 return pNew;
358}
359
371void Cec5_AddClausesMux( Gia_Man_t * p, Gia_Obj_t * pNode, sat_solver * pSat )
372{
373 int fPolarFlip = 0;
374 Gia_Obj_t * pNodeI, * pNodeT, * pNodeE;
375 int pLits[4], RetValue, VarF, VarI, VarT, VarE, fCompT, fCompE;
376
377 assert( !Gia_IsComplement( pNode ) );
378 assert( pNode->fMark0 );
379 // get nodes (I = if, T = then, E = else)
380 pNodeI = Gia_ObjRecognizeMux( pNode, &pNodeT, &pNodeE );
381 // get the variable numbers
382 VarF = Cec5_ObjSatId(p, pNode);
383 VarI = Cec5_ObjSatId(p, pNodeI);
384 VarT = Cec5_ObjSatId(p, Gia_Regular(pNodeT));
385 VarE = Cec5_ObjSatId(p, Gia_Regular(pNodeE));
386 // get the complementation flags
387 fCompT = Gia_IsComplement(pNodeT);
388 fCompE = Gia_IsComplement(pNodeE);
389
390 // f = ITE(i, t, e)
391
392 // i' + t' + f
393 // i' + t + f'
394 // i + e' + f
395 // i + e + f'
396
397 // create four clauses
398 pLits[0] = Abc_Var2Lit(VarI, 1);
399 pLits[1] = Abc_Var2Lit(VarT, 1^fCompT);
400 pLits[2] = Abc_Var2Lit(VarF, 0);
401 if ( fPolarFlip )
402 {
403 if ( pNodeI->fPhase ) pLits[0] = Abc_LitNot( pLits[0] );
404 if ( Gia_Regular(pNodeT)->fPhase ) pLits[1] = Abc_LitNot( pLits[1] );
405 if ( pNode->fPhase ) pLits[2] = Abc_LitNot( pLits[2] );
406 }
407 RetValue = sat_solver_addclause( pSat, pLits, 3 );
408 assert( RetValue );
409 pLits[0] = Abc_Var2Lit(VarI, 1);
410 pLits[1] = Abc_Var2Lit(VarT, 0^fCompT);
411 pLits[2] = Abc_Var2Lit(VarF, 1);
412 if ( fPolarFlip )
413 {
414 if ( pNodeI->fPhase ) pLits[0] = Abc_LitNot( pLits[0] );
415 if ( Gia_Regular(pNodeT)->fPhase ) pLits[1] = Abc_LitNot( pLits[1] );
416 if ( pNode->fPhase ) pLits[2] = Abc_LitNot( pLits[2] );
417 }
418 RetValue = sat_solver_addclause( pSat, pLits, 3 );
419 assert( RetValue );
420 pLits[0] = Abc_Var2Lit(VarI, 0);
421 pLits[1] = Abc_Var2Lit(VarE, 1^fCompE);
422 pLits[2] = Abc_Var2Lit(VarF, 0);
423 if ( fPolarFlip )
424 {
425 if ( pNodeI->fPhase ) pLits[0] = Abc_LitNot( pLits[0] );
426 if ( Gia_Regular(pNodeE)->fPhase ) pLits[1] = Abc_LitNot( pLits[1] );
427 if ( pNode->fPhase ) pLits[2] = Abc_LitNot( pLits[2] );
428 }
429 RetValue = sat_solver_addclause( pSat, pLits, 3 );
430 assert( RetValue );
431 pLits[0] = Abc_Var2Lit(VarI, 0);
432 pLits[1] = Abc_Var2Lit(VarE, 0^fCompE);
433 pLits[2] = Abc_Var2Lit(VarF, 1);
434 if ( fPolarFlip )
435 {
436 if ( pNodeI->fPhase ) pLits[0] = Abc_LitNot( pLits[0] );
437 if ( Gia_Regular(pNodeE)->fPhase ) pLits[1] = Abc_LitNot( pLits[1] );
438 if ( pNode->fPhase ) pLits[2] = Abc_LitNot( pLits[2] );
439 }
440 RetValue = sat_solver_addclause( pSat, pLits, 3 );
441 assert( RetValue );
442
443 // two additional clauses
444 // t' & e' -> f'
445 // t & e -> f
446
447 // t + e + f'
448 // t' + e' + f
449
450 if ( VarT == VarE )
451 {
452// assert( fCompT == !fCompE );
453 return;
454 }
455
456 pLits[0] = Abc_Var2Lit(VarT, 0^fCompT);
457 pLits[1] = Abc_Var2Lit(VarE, 0^fCompE);
458 pLits[2] = Abc_Var2Lit(VarF, 1);
459 if ( fPolarFlip )
460 {
461 if ( Gia_Regular(pNodeT)->fPhase ) pLits[0] = Abc_LitNot( pLits[0] );
462 if ( Gia_Regular(pNodeE)->fPhase ) pLits[1] = Abc_LitNot( pLits[1] );
463 if ( pNode->fPhase ) pLits[2] = Abc_LitNot( pLits[2] );
464 }
465 RetValue = sat_solver_addclause( pSat, pLits, 3 );
466 assert( RetValue );
467 pLits[0] = Abc_Var2Lit(VarT, 1^fCompT);
468 pLits[1] = Abc_Var2Lit(VarE, 1^fCompE);
469 pLits[2] = Abc_Var2Lit(VarF, 0);
470 if ( fPolarFlip )
471 {
472 if ( Gia_Regular(pNodeT)->fPhase ) pLits[0] = Abc_LitNot( pLits[0] );
473 if ( Gia_Regular(pNodeE)->fPhase ) pLits[1] = Abc_LitNot( pLits[1] );
474 if ( pNode->fPhase ) pLits[2] = Abc_LitNot( pLits[2] );
475 }
476 RetValue = sat_solver_addclause( pSat, pLits, 3 );
477 assert( RetValue );
478}
479void Cec5_AddClausesSuper( Gia_Man_t * p, Gia_Obj_t * pNode, Vec_Ptr_t * vSuper, sat_solver * pSat )
480{
481 int fPolarFlip = 0;
482 Gia_Obj_t * pFanin;
483 int * pLits, nLits, RetValue, i;
484 assert( !Gia_IsComplement(pNode) );
485 assert( Gia_ObjIsAnd( pNode ) );
486 // create storage for literals
487 nLits = Vec_PtrSize(vSuper) + 1;
488 pLits = ABC_ALLOC( int, nLits );
489 // suppose AND-gate is A & B = C
490 // add !A => !C or A + !C
491 Vec_PtrForEachEntry( Gia_Obj_t *, vSuper, pFanin, i )
492 {
493 pLits[0] = Abc_Var2Lit(Cec5_ObjSatId(p, Gia_Regular(pFanin)), Gia_IsComplement(pFanin));
494 pLits[1] = Abc_Var2Lit(Cec5_ObjSatId(p, pNode), 1);
495 if ( fPolarFlip )
496 {
497 if ( Gia_Regular(pFanin)->fPhase ) pLits[0] = Abc_LitNot( pLits[0] );
498 if ( pNode->fPhase ) pLits[1] = Abc_LitNot( pLits[1] );
499 }
500 RetValue = sat_solver_addclause( pSat, pLits, 2 );
501 assert( RetValue );
502 }
503 // add A & B => C or !A + !B + C
504 Vec_PtrForEachEntry( Gia_Obj_t *, vSuper, pFanin, i )
505 {
506 pLits[i] = Abc_Var2Lit(Cec5_ObjSatId(p, Gia_Regular(pFanin)), !Gia_IsComplement(pFanin));
507 if ( fPolarFlip )
508 {
509 if ( Gia_Regular(pFanin)->fPhase ) pLits[i] = Abc_LitNot( pLits[i] );
510 }
511 }
512 pLits[nLits-1] = Abc_Var2Lit(Cec5_ObjSatId(p, pNode), 0);
513 if ( fPolarFlip )
514 {
515 if ( pNode->fPhase ) pLits[nLits-1] = Abc_LitNot( pLits[nLits-1] );
516 }
517 RetValue = sat_solver_addclause( pSat, pLits, nLits );
518 assert( RetValue );
519 ABC_FREE( pLits );
520}
521
533void Cec5_CollectSuper_rec( Gia_Obj_t * pObj, Vec_Ptr_t * vSuper, int fFirst, int fUseMuxes )
534{
535 // if the new node is complemented or a PI, another gate begins
536 if ( Gia_IsComplement(pObj) || Gia_ObjIsCi(pObj) ||
537 (!fFirst && Gia_ObjValue(pObj) > 1) ||
538 (fUseMuxes && pObj->fMark0) )
539 {
540 Vec_PtrPushUnique( vSuper, pObj );
541 return;
542 }
543 // go through the branches
544 Cec5_CollectSuper_rec( Gia_ObjChild0(pObj), vSuper, 0, fUseMuxes );
545 Cec5_CollectSuper_rec( Gia_ObjChild1(pObj), vSuper, 0, fUseMuxes );
546}
547void Cec5_CollectSuper( Gia_Obj_t * pObj, int fUseMuxes, Vec_Ptr_t * vSuper )
548{
549 assert( !Gia_IsComplement(pObj) );
550 assert( !Gia_ObjIsCi(pObj) );
551 Vec_PtrClear( vSuper );
552 Cec5_CollectSuper_rec( pObj, vSuper, 1, fUseMuxes );
553}
554void Cec5_ObjAddToFrontier( Gia_Man_t * p, Gia_Obj_t * pObj, Vec_Ptr_t * vFrontier, sat_solver * pSat )
555{
556 assert( !Gia_IsComplement(pObj) );
557 assert( !Gia_ObjIsConst0(pObj) );
558 if ( Cec5_ObjSatId(p, pObj) >= 0 )
559 return;
560 assert( Cec5_ObjSatId(p, pObj) == -1 );
561 Cec5_ObjSetSatId( p, pObj, sat_solver_addvar(pSat) );
562 if ( Gia_ObjIsAnd(pObj) )
563 Vec_PtrPush( vFrontier, pObj );
564}
565int Cec5_ObjGetCnfVar( Cec5_Man_t * p, int iObj )
566{
567 int fUseSimple = 1; // enable simple CNF
568 int fUseMuxes = 1; // enable MUXes when using complex CNF
569 Gia_Obj_t * pNode, * pFanin;
570 Gia_Obj_t * pObj = Gia_ManObj(p->pNew, iObj);
571 int i, k;
572 // quit if CNF is ready
573 if ( Cec5_ObjSatId(p->pNew,pObj) >= 0 )
574 return Cec5_ObjSatId(p->pNew,pObj);
575
576 assert( iObj > 0 );
577 if ( Gia_ObjIsCi(pObj) )
578 return Cec5_ObjSetSatId( p->pNew, pObj, sat_solver_addvar(p->pSat) );
579 assert( Gia_ObjIsAnd(pObj) );
580 if ( fUseSimple )
581 {
582 Gia_Obj_t * pFan0, * pFan1;
583 //if ( Gia_ObjRecognizeExor(pObj, &pFan0, &pFan1) )
584 // printf( "%d", (Gia_IsComplement(pFan1) << 1) + Gia_IsComplement(pFan0) );
585 if ( p->pNew->pMuxes == NULL && Gia_ObjRecognizeExor(pObj, &pFan0, &pFan1) && Gia_IsComplement(pFan0) == Gia_IsComplement(pFan1) )
586 {
587 int iVar0 = Cec5_ObjGetCnfVar( p, Gia_ObjId(p->pNew, Gia_Regular(pFan0)) );
588 int iVar1 = Cec5_ObjGetCnfVar( p, Gia_ObjId(p->pNew, Gia_Regular(pFan1)) );
589 int iVar = Cec5_ObjSetSatId( p->pNew, pObj, sat_solver_addvar(p->pSat) );
590 if ( p->pPars->jType < 2 )
591 sat_solver_add_xor( p->pSat, iVar, iVar0, iVar1, 0 );
592 if ( p->pPars->jType > 0 )
593 {
594 int Lit0 = Abc_Var2Lit( iVar0, 0 );
595 int Lit1 = Abc_Var2Lit( iVar1, 0 );
596 if ( Lit0 < Lit1 )
597 Lit1 ^= Lit0, Lit0 ^= Lit1, Lit1 ^= Lit0;
598 assert( Lit0 > Lit1 );
599 sat_solver_set_var_fanin_lit( p->pSat, iVar, Lit0, Lit1 );
600 p->nGates[1]++;
601 }
602 }
603 else
604 {
605 int iVar0 = Cec5_ObjGetCnfVar( p, Gia_ObjFaninId0(pObj, iObj) );
606 int iVar1 = Cec5_ObjGetCnfVar( p, Gia_ObjFaninId1(pObj, iObj) );
607 int iVar = Cec5_ObjSetSatId( p->pNew, pObj, sat_solver_addvar(p->pSat) );
608 if ( p->pPars->jType < 2 )
609 {
610 if ( Gia_ObjIsXor(pObj) )
611 sat_solver_add_xor( p->pSat, iVar, iVar0, iVar1, Gia_ObjFaninC0(pObj) ^ Gia_ObjFaninC1(pObj) );
612 else
613 sat_solver_add_and( p->pSat, iVar, iVar0, iVar1, Gia_ObjFaninC0(pObj), Gia_ObjFaninC1(pObj), 0 );
614 }
615 if ( p->pPars->jType > 0 )
616 {
617 int Lit0 = Abc_Var2Lit( iVar0, Gia_ObjFaninC0(pObj) );
618 int Lit1 = Abc_Var2Lit( iVar1, Gia_ObjFaninC1(pObj) );
619 if ( (Lit0 > Lit1) ^ Gia_ObjIsXor(pObj) )
620 Lit1 ^= Lit0, Lit0 ^= Lit1, Lit1 ^= Lit0;
621 sat_solver_set_var_fanin_lit( p->pSat, iVar, Lit0, Lit1 );
622 p->nGates[Gia_ObjIsXor(pObj)]++;
623 }
624 }
625 return Cec5_ObjSatId( p->pNew, pObj );
626 }
627 assert( !Gia_ObjIsXor(pObj) );
628 // start the frontier
629 Vec_PtrClear( p->vFrontier );
630 Cec5_ObjAddToFrontier( p->pNew, pObj, p->vFrontier, p->pSat );
631 // explore nodes in the frontier
632 Vec_PtrForEachEntry( Gia_Obj_t *, p->vFrontier, pNode, i )
633 {
634 // create the supergate
635 assert( Cec5_ObjSatId(p->pNew,pNode) >= 0 );
636 if ( fUseMuxes && pNode->fMark0 )
637 {
638 Vec_PtrClear( p->vFanins );
639 Vec_PtrPushUnique( p->vFanins, Gia_ObjFanin0( Gia_ObjFanin0(pNode) ) );
640 Vec_PtrPushUnique( p->vFanins, Gia_ObjFanin0( Gia_ObjFanin1(pNode) ) );
641 Vec_PtrPushUnique( p->vFanins, Gia_ObjFanin1( Gia_ObjFanin0(pNode) ) );
642 Vec_PtrPushUnique( p->vFanins, Gia_ObjFanin1( Gia_ObjFanin1(pNode) ) );
643 Vec_PtrForEachEntry( Gia_Obj_t *, p->vFanins, pFanin, k )
644 Cec5_ObjAddToFrontier( p->pNew, Gia_Regular(pFanin), p->vFrontier, p->pSat );
645 Cec5_AddClausesMux( p->pNew, pNode, p->pSat );
646 }
647 else
648 {
649 Cec5_CollectSuper( pNode, fUseMuxes, p->vFanins );
650 Vec_PtrForEachEntry( Gia_Obj_t *, p->vFanins, pFanin, k )
651 Cec5_ObjAddToFrontier( p->pNew, Gia_Regular(pFanin), p->vFrontier, p->pSat );
652 Cec5_AddClausesSuper( p->pNew, pNode, p->vFanins, p->pSat );
653 }
654 assert( Vec_PtrSize(p->vFanins) > 1 );
655 }
656 return Cec5_ObjSatId(p->pNew,pObj);
657}
658
659
671static inline word * Cec5_ObjSim( Gia_Man_t * p, int iObj )
672{
673 return Vec_WrdEntryP( p->vSims, p->nSimWords * iObj );
674}
675static inline int Cec5_ObjSimEqual( Gia_Man_t * p, int iObj0, int iObj1 )
676{
677 int w;
678 word * pSim0 = Cec5_ObjSim( p, iObj0 );
679 word * pSim1 = Cec5_ObjSim( p, iObj1 );
680 if ( (pSim0[0] & 1) == (pSim1[0] & 1) )
681 {
682 for ( w = 0; w < p->nSimWords; w++ )
683 if ( pSim0[w] != pSim1[w] )
684 return 0;
685 return 1;
686 }
687 else
688 {
689 for ( w = 0; w < p->nSimWords; w++ )
690 if ( pSim0[w] != ~pSim1[w] )
691 return 0;
692 return 1;
693 }
694}
695int Cec5_ManSimHashKey( word * pSim, int nSims, int nTableSize )
696{
697 static int s_Primes[16] = {
698 1291, 1699, 1999, 2357, 2953, 3313, 3907, 4177,
699 4831, 5147, 5647, 6343, 6899, 7103, 7873, 8147 };
700 unsigned uHash = 0, * pSimU = (unsigned *)pSim;
701 int i, nSimsU = 2 * nSims;
702 if ( pSimU[0] & 1 )
703 for ( i = 0; i < nSimsU; i++ )
704 uHash ^= ~pSimU[i] * s_Primes[i & 0xf];
705 else
706 for ( i = 0; i < nSimsU; i++ )
707 uHash ^= pSimU[i] * s_Primes[i & 0xf];
708 return (int)(uHash % nTableSize);
709
710}
711void Cec5_RefineOneClassIter( Gia_Man_t * p, int iRepr )
712{
713 int iObj, iPrev = iRepr, iPrev2, iRepr2;
714 assert( Gia_ObjRepr(p, iRepr) == GIA_VOID );
715 assert( Gia_ObjNext(p, iRepr) > 0 );
716 Gia_ClassForEachObj1( p, iRepr, iRepr2 )
717 if ( Cec5_ObjSimEqual(p, iRepr, iRepr2) )
718 iPrev = iRepr2;
719 else
720 break;
721 if ( iRepr2 <= 0 ) // no refinement
722 return;
723 // relink remaining nodes of the class
724 // nodes that are equal to iRepr, remain in the class of iRepr
725 // nodes that are not equal to iRepr, move to the class of iRepr2
726 Gia_ObjSetRepr( p, iRepr2, GIA_VOID );
727 assert( !Gia_ObjProved(p,iRepr2) );
728 iPrev2 = iRepr2;
729 for ( iObj = Gia_ObjNext(p, iRepr2); iObj > 0; iObj = Gia_ObjNext(p, iObj) )
730 {
731 if ( Cec5_ObjSimEqual(p, iRepr, iObj) ) // remains with iRepr
732 {
733 Gia_ObjSetNext( p, iPrev, iObj );
734 iPrev = iObj;
735 }
736 else // moves to iRepr2
737 {
738 Gia_ObjSetRepr( p, iObj, iRepr2 );
739 Gia_ObjSetNext( p, iPrev2, iObj );
740 iPrev2 = iObj;
741 }
742 }
743 Gia_ObjSetNext( p, iPrev, -1 );
744 Gia_ObjSetNext( p, iPrev2, -1 );
745 // refine incrementally
746 if ( Gia_ObjNext(p, iRepr2) > 0 )
747 Cec5_RefineOneClassIter( p, iRepr2 );
748}
749void Cec5_RefineOneClass( Gia_Man_t * p, Cec5_Man_t * pMan, Vec_Int_t * vNodes )
750{
751 int k, iObj, Bin;
752 Vec_IntClear( pMan->vRefBins );
753 Vec_IntForEachEntryReverse( vNodes, iObj, k )
754 {
755 int Key = Cec5_ManSimHashKey( Cec5_ObjSim(p, iObj), p->nSimWords, pMan->nTableSize );
756 assert( Key >= 0 && Key < pMan->nTableSize );
757 if ( pMan->pTable[Key] == -1 )
758 Vec_IntPush( pMan->vRefBins, Key );
759 p->pNexts[iObj] = pMan->pTable[Key];
760 pMan->pTable[Key] = iObj;
761 }
762 Vec_IntForEachEntry( pMan->vRefBins, Bin, k )
763 {
764 int iRepr = pMan->pTable[Bin];
765 pMan->pTable[Bin] = -1;
766 assert( p->pReprs[iRepr].iRepr == GIA_VOID );
767 assert( p->pNexts[iRepr] != 0 );
768 assert( !Gia_ObjProved(p,iRepr) );
769 if ( p->pNexts[iRepr] == -1 )
770 continue;
771 for ( iObj = p->pNexts[iRepr]; iObj > 0; iObj = p->pNexts[iObj] )
772 p->pReprs[iObj].iRepr = iRepr;
773 Cec5_RefineOneClassIter( p, iRepr );
774 }
775 Vec_IntClear( pMan->vRefBins );
776}
777void Cec5_RefineClasses( Gia_Man_t * p, Cec5_Man_t * pMan, Vec_Int_t * vClasses )
778{
779 if ( Vec_IntSize(pMan->vRefClasses) == 0 )
780 return;
781 if ( Vec_IntSize(pMan->vRefNodes) > 0 )
782 Cec5_RefineOneClass( p, pMan, pMan->vRefNodes );
783 else
784 {
785 int i, k, iObj, iRepr;
786 Vec_IntForEachEntry( pMan->vRefClasses, iRepr, i )
787 {
788 assert( p->pReprs[iRepr].fColorA );
789 p->pReprs[iRepr].fColorA = 0;
790 Vec_IntClear( pMan->vRefNodes );
791 Vec_IntPush( pMan->vRefNodes, iRepr );
792 Gia_ClassForEachObj1( p, iRepr, k )
793 Vec_IntPush( pMan->vRefNodes, k );
794 Vec_IntForEachEntry( pMan->vRefNodes, iObj, k )
795 {
796 p->pReprs[iObj].iRepr = GIA_VOID;
797 p->pNexts[iObj] = -1;
798 }
799 Cec5_RefineOneClass( p, pMan, pMan->vRefNodes );
800 }
801 }
802 Vec_IntClear( pMan->vRefClasses );
803 Vec_IntClear( pMan->vRefNodes );
804}
805void Cec5_RefineInit( Gia_Man_t * p, Cec5_Man_t * pMan )
806{
807 Gia_Obj_t * pObj; int i;
808 if( pMan->fEec ){
809 assert( p->pReprs );
810 assert( p->pNexts );
811 } else {
812 ABC_FREE( p->pReprs );
813 ABC_FREE( p->pNexts );
814 p->pReprs = ABC_CALLOC( Gia_Rpr_t, Gia_ManObjNum(p) );
815 p->pNexts = ABC_FALLOC( int, Gia_ManObjNum(p) );
816 }
817
818 pMan->nTableSize = Abc_PrimeCudd( Gia_ManObjNum(p) );
819 pMan->pTable = ABC_FALLOC( int, pMan->nTableSize );
820 pMan->vRefNodes = Vec_IntAlloc( Gia_ManObjNum(p) );
821
822 pMan->vRefBins = Vec_IntAlloc( Gia_ManObjNum(p)/2 );
823 pMan->vRefClasses = Vec_IntAlloc( Gia_ManObjNum(p)/2 );
824
825 if( pMan->fEec ) return;
826
827 Gia_ManForEachObj( p, pObj, i )
828 {
829 p->pReprs[i].iRepr = GIA_VOID;
830 if ( !Gia_ObjIsCo(pObj) && (!pMan->pPars->nLevelMax || Gia_ObjLevel(p, pObj) <= pMan->pPars->nLevelMax) )
831 Vec_IntPush( pMan->vRefNodes, i );
832 }
833
834 Vec_IntPush( pMan->vRefClasses, 0 );
835}
836
837
849static inline void Cec5_ObjSimSetInputBit( Gia_Man_t * p, int iObj, int Bit )
850{
851 word * pSim = Cec5_ObjSim( p, iObj );
852 if ( Abc_InfoHasBit( (unsigned*)pSim, p->iPatsPi ) != Bit )
853 Abc_InfoXorBit( (unsigned*)pSim, p->iPatsPi );
854}
855static inline int Cec5_ObjSimGetInputBit( Gia_Man_t * p, int iObj )
856{
857 word * pSim = Cec5_ObjSim( p, iObj );
858 return Abc_InfoHasBit( (unsigned*)pSim, p->iPatsPi );
859}
860static inline void Cec5_ObjSimRo( Gia_Man_t * p, int iObj )
861{
862 int w;
863 word * pSimRo = Cec5_ObjSim( p, iObj );
864 word * pSimRi = Cec5_ObjSim( p, Gia_ObjRoToRiId(p, iObj) );
865 for ( w = 0; w < p->nSimWords; w++ )
866 pSimRo[w] = pSimRi[w];
867}
868static inline void Cec5_ObjSimCo( Gia_Man_t * p, int iObj )
869{
870 int w;
871 Gia_Obj_t * pObj = Gia_ManObj( p, iObj );
872 word * pSimCo = Cec5_ObjSim( p, iObj );
873 word * pSimDri = Cec5_ObjSim( p, Gia_ObjFaninId0(pObj, iObj) );
874 if ( Gia_ObjFaninC0(pObj) )
875 for ( w = 0; w < p->nSimWords; w++ )
876 pSimCo[w] = ~pSimDri[w];
877 else
878 for ( w = 0; w < p->nSimWords; w++ )
879 pSimCo[w] = pSimDri[w];
880}
881static inline void Cec5_ObjSimAnd( Gia_Man_t * p, Cec5_Man_t * pMan, int iObj )
882{
883 int w;
884 Gia_Obj_t * pObj = Gia_ManObj( p, iObj );
885 word * pSim = Cec5_ObjSim( p, iObj );
886 word * pSim0 = Cec5_ObjSim( p, Gia_ObjFaninId0(pObj, iObj) );
887 word * pSim1 = Cec5_ObjSim( p, Gia_ObjFaninId1(pObj, iObj) );
888 if ( Gia_ObjFaninC0(pObj) && Gia_ObjFaninC1(pObj) )
889 for ( w = pMan->simStart; w < pMan->simBound; w++ )
890 pSim[w] = ~pSim0[w] & ~pSim1[w];
891 else if ( Gia_ObjFaninC0(pObj) && !Gia_ObjFaninC1(pObj) )
892 for ( w = pMan->simStart; w < pMan->simBound; w++ )
893 pSim[w] = ~pSim0[w] & pSim1[w];
894 else if ( !Gia_ObjFaninC0(pObj) && Gia_ObjFaninC1(pObj) )
895 for ( w = pMan->simStart; w < pMan->simBound; w++ )
896 pSim[w] = pSim0[w] & ~pSim1[w];
897 else
898 for ( w = pMan->simStart; w < pMan->simBound; w++ )
899 pSim[w] = pSim0[w] & pSim1[w];
900}
901static inline void Cec5_ObjSimXor( Gia_Man_t * p, Cec5_Man_t * pMan, int iObj )
902{
903 int w;
904 Gia_Obj_t * pObj = Gia_ManObj( p, iObj );
905 word * pSim = Cec5_ObjSim( p, iObj );
906 word * pSim0 = Cec5_ObjSim( p, Gia_ObjFaninId0(pObj, iObj) );
907 word * pSim1 = Cec5_ObjSim( p, Gia_ObjFaninId1(pObj, iObj) );
908 if ( Gia_ObjFaninC0(pObj) ^ Gia_ObjFaninC1(pObj) )
909 for ( w = pMan->simStart; w < pMan->simBound; w++ )
910 pSim[w] = ~pSim0[w] ^ pSim1[w];
911 else
912 for ( w = pMan->simStart; w < pMan->simBound; w++ )
913 pSim[w] = pSim0[w] ^ pSim1[w];
914}
915static inline void Cec5_ObjSimCi( Gia_Man_t * p, int iObj )
916{
917 int w;
918 word * pSim = Cec5_ObjSim( p, iObj );
919 for ( w = 0; w < p->nSimWords; w++ )
920 pSim[w] = Abc_RandomW( 0 );
921 pSim[0] <<= 1;
922}
923static inline void Cec5_ObjClearSimCi( Gia_Man_t * p, int iObj )
924{
925 int w;
926 word * pSim = Cec5_ObjSim( p, iObj );
927 for ( w = 0; w < p->nSimWords; w++ )
928 pSim[w] = 0;
929}
930void Cec5_ManSimulateCis( Gia_Man_t * p )
931{
932 int i, Id;
933 Gia_ManForEachCiId( p, Id, i )
934 Cec5_ObjSimCi( p, Id );
935 p->iPatsPi = 0;
936}
937void Cec5_ManClearCis( Gia_Man_t * p )
938{
939 int i, Id;
940 Gia_ManForEachCiId( p, Id, i )
941 Cec5_ObjClearSimCi( p, Id );
942 p->iPatsPi = 0;
943}
944Abc_Cex_t * Cec5_ManDeriveCex( Gia_Man_t * p, int iOut, int iPat )
945{
946 Abc_Cex_t * pCex;
947 int i, Id;
948 pCex = Abc_CexAlloc( 0, Gia_ManCiNum(p), 1 );
949 pCex->iPo = iOut;
950 if ( iPat == -1 )
951 return pCex;
952 Gia_ManForEachCiId( p, Id, i )
953 if ( Abc_InfoHasBit((unsigned *)Cec5_ObjSim(p, Id), iPat) )
954 Abc_InfoSetBit( pCex->pData, i );
955 return pCex;
956}
957int Cec5_ManSimulateCos( Gia_Man_t * p )
958{
959 int i, Id;
960 // check outputs and generate CEX if they fail
961 Gia_ManForEachCoId( p, Id, i )
962 {
963 Cec5_ObjSimCo( p, Id );
964 if ( Cec5_ObjSimEqual(p, Id, 0) )
965 continue;
966 p->pCexSeq = Cec5_ManDeriveCex( p, i, Abc_TtFindFirstBit2(Cec5_ObjSim(p, Id), p->nSimWords) );
967 return 0;
968 }
969 return 1;
970}
971void Cec5_ManSimulate( Gia_Man_t * p, Cec5_Man_t * pMan )
972{
973 abctime clk = Abc_Clock();
974 Gia_Obj_t * pObj; int i;
975 pMan->nSimulates++;
976 if ( pMan->pTable == NULL )
977 Cec5_RefineInit( p, pMan );
978 else
979 assert( Vec_IntSize(pMan->vRefClasses) == 0 );
980
981 pMan->simStart = pMan->simGlobalTop;
982 Gia_ManForEachAnd( p, pObj, i )
983 {
984 int iRepr = Gia_ObjRepr( p, i );
985 if ( Gia_ObjIsXor(pObj) )
986 Cec5_ObjSimXor( p, pMan, i );
987 else
988 Cec5_ObjSimAnd( p, pMan, i );
989 if ( iRepr == GIA_VOID || p->pReprs[iRepr].fColorA || Cec5_ObjSimEqual(p, iRepr, i) )
990 continue;
991 p->pReprs[iRepr].fColorA = 1;
992 Vec_IntPush( pMan->vRefClasses, iRepr );
993 }
994 pMan->simStart = 0;
995 pMan->timeSim += Abc_Clock() - clk;
996 clk = Abc_Clock();
997 Cec5_RefineClasses( p, pMan, pMan->vRefClasses );
998 pMan->timeRefine += Abc_Clock() - clk;
999}
1000void Cec5_ManSimulate_rec( Gia_Man_t * p, Cec5_Man_t * pMan, int iObj )
1001{
1002 Gia_Obj_t * pObj;
1003 int progress;
1004 if ( !iObj || (progress = Vec_IntEntry(pMan->vCexStamps, iObj)) == pMan->simTravId )
1005 return;
1006 Vec_IntWriteEntry( pMan->vCexStamps, iObj, pMan->simTravId );
1007 pObj = Gia_ManObj(p, iObj);
1008 if ( Gia_ObjIsCi(pObj) )
1009 return;
1010 assert( Gia_ObjIsAnd(pObj) );
1011 Cec5_ManSimulate_rec( p, pMan, Gia_ObjFaninId0(pObj, iObj) );
1012 Cec5_ManSimulate_rec( p, pMan, Gia_ObjFaninId1(pObj, iObj) );
1013 pMan->simStart = progress * pMan->LocalBatchSize / (sizeof(word)<<3);
1014 if ( Gia_ObjIsXor(pObj) )
1015 Cec5_ObjSimXor( p, pMan, iObj );
1016 else
1017 Cec5_ObjSimAnd( p, pMan, iObj );
1018 pMan->simStart = 0;
1019}
1020void Cec5_ManSimAlloc( Gia_Man_t * p, int nWords, int fPrep )
1021{
1022 if( !fPrep ){
1023 Vec_WrdFreeP( &p->vSimsPi );
1024 p->vSimsPi = Vec_WrdStart( (Gia_ManCiNum(p) + 1) * nWords );
1025 }
1026 Vec_WrdFreeP( &p->vSims );
1027 p->vSims = Vec_WrdStart( Gia_ManObjNum(p) * nWords );
1028 p->nSimWords = nWords;
1029}
1030
1031
1043void Cec5_ManPrintTfiConeStats( Gia_Man_t * p )
1044{
1045 Vec_Int_t * vRoots = Vec_IntAlloc( 100 );
1046 Vec_Int_t * vNodes = Vec_IntAlloc( 100 );
1047 Vec_Int_t * vLeaves = Vec_IntAlloc( 100 );
1048 int i, k;
1049 Gia_ManForEachClass0( p, i )
1050 {
1051 Vec_IntClear( vRoots );
1052 if ( i % 100 != 0 )
1053 continue;
1054 Vec_IntPush( vRoots, i );
1055 Gia_ClassForEachObj1( p, i, k )
1056 Vec_IntPush( vRoots, k );
1057 Gia_ManCollectTfi( p, vRoots, vNodes );
1058 printf( "Class %6d : ", i );
1059 printf( "Roots = %6d ", Vec_IntSize(vRoots) );
1060 printf( "Nodes = %6d ", Vec_IntSize(vNodes) );
1061 printf( "\n" );
1062 }
1063 Vec_IntFree( vRoots );
1064 Vec_IntFree( vNodes );
1065 Vec_IntFree( vLeaves );
1066}
1067void Cec5_ManPrintStats( Gia_Man_t * p, Cec_ParFra_t * pPars, Cec5_Man_t * pMan, int fSim )
1068{
1069 static abctime clk = 0;
1070 abctime clkThis = 0;
1071 int i, nLits, Counter = 0, Counter0 = 0, CounterX = 0;
1072 if ( !pPars->fVerbose )
1073 return;
1074 if ( pMan->nItersSim + pMan->nItersSat )
1075 clkThis = Abc_Clock() - clk;
1076 clk = Abc_Clock();
1077 for ( i = 0; i < Gia_ManObjNum(p); i++ )
1078 {
1079 if ( Gia_ObjIsHead(p, i) )
1080 Counter++;
1081 else if ( Gia_ObjIsConst(p, i) )
1082 Counter0++;
1083 else if ( Gia_ObjIsNone(p, i) )
1084 CounterX++;
1085 }
1086 nLits = Gia_ManObjNum(p) - Counter - CounterX;
1087 if ( fSim )
1088 {
1089 printf( "Sim %4d : ", pMan->nItersSim++ + pMan->nItersSat );
1090 printf( "%6.2f %% ", 100.0*nLits/Gia_ManCandNum(p) );
1091 }
1092 else
1093 {
1094 printf( "SAT %4d : ", pMan->nItersSim + pMan->nItersSat++ );
1095 printf( "%6.2f %% ", 100.0*pMan->nAndNodes/Gia_ManAndNum(p) );
1096 }
1097 printf( "P =%7d ", pMan ? pMan->nSatUnsat : 0 );
1098 printf( "D =%7d ", pMan ? pMan->nSatSat : 0 );
1099 printf( "F =%8d ", pMan ? pMan->nSatUndec : 0 );
1100 //printf( "Last =%6d ", pMan ? pMan->iLastConst : 0 );
1101 Abc_Print( 1, "cst =%9d cls =%8d lit =%9d ", Counter0, Counter, nLits );
1102 Abc_PrintTime( 1, "Time", clkThis );
1103}
1104void Cec5_ManPrintClasses2( Gia_Man_t * p )
1105{
1106 int i, k;
1107 Gia_ManForEachClass0( p, i )
1108 {
1109 printf( "Class %d : ", i );
1110 Gia_ClassForEachObj1( p, i, k )
1111 printf( "%d ", k );
1112 printf( "\n" );
1113 }
1114}
1115void Cec5_ManPrintClasses( Gia_Man_t * p )
1116{
1117 int k, Count = 0;
1118 Gia_ClassForEachObj1( p, 0, k )
1119 Count++;
1120 printf( "Const0 class has %d entries.\n", Count );
1121}
1122
1123
1135int Cec5_ManVerify_rec( Gia_Man_t * p, int iObj, sat_solver * pSat )
1136{
1137 int Value0, Value1;
1138 Gia_Obj_t * pObj = Gia_ManObj( p, iObj );
1139 if ( iObj == 0 ) return 0;
1140 if ( Gia_ObjIsTravIdCurrentId(p, iObj) )
1141 return pObj->fMark1;
1142 Gia_ObjSetTravIdCurrentId(p, iObj);
1143 if ( Gia_ObjIsCi(pObj) )
1144 return pObj->fMark1 = sat_solver_read_cex_varvalue(pSat, Cec5_ObjSatId(p, pObj));
1145 assert( Gia_ObjIsAnd(pObj) );
1146 Value0 = Cec5_ManVerify_rec( p, Gia_ObjFaninId0(pObj, iObj), pSat ) ^ Gia_ObjFaninC0(pObj);
1147 Value1 = Cec5_ManVerify_rec( p, Gia_ObjFaninId1(pObj, iObj), pSat ) ^ Gia_ObjFaninC1(pObj);
1148 return pObj->fMark1 = Gia_ObjIsXor(pObj) ? Value0 ^ Value1 : Value0 & Value1;
1149}
1150void Cec5_ManVerify( Gia_Man_t * p, int iObj0, int iObj1, int fPhase, sat_solver * pSat )
1151{
1152 int Value0, Value1;
1153 Gia_ManIncrementTravId( p );
1154 Value0 = Cec5_ManVerify_rec( p, iObj0, pSat );
1155 Value1 = Cec5_ManVerify_rec( p, iObj1, pSat );
1156 if ( (Value0 ^ Value1) == fPhase )
1157 printf( "CEX verification FAILED for obj %d and obj %d.\n", iObj0, iObj1 );
1158// else
1159// printf( "CEX verification succeeded for obj %d and obj %d.\n", iObj0, iObj1 );;
1160}
1161
1162
1174int Cec5_ManCexVerify_rec( Gia_Man_t * p, int iObj )
1175{
1176 int Value0, Value1;
1177 Gia_Obj_t * pObj = Gia_ManObj( p, iObj );
1178 if ( iObj == 0 ) return 0;
1179 if ( Gia_ObjIsTravIdCurrentId(p, iObj) )
1180 return pObj->fMark1;
1181 Gia_ObjSetTravIdCurrentId(p, iObj);
1182 if ( Gia_ObjIsCi(pObj) )
1183 return pObj->fMark1 = Cec5_ObjSimGetInputBit(p, iObj);
1184 assert( Gia_ObjIsAnd(pObj) );
1185 Value0 = Cec5_ManCexVerify_rec( p, Gia_ObjFaninId0(pObj, iObj) ) ^ Gia_ObjFaninC0(pObj);
1186 Value1 = Cec5_ManCexVerify_rec( p, Gia_ObjFaninId1(pObj, iObj) ) ^ Gia_ObjFaninC1(pObj);
1187 return pObj->fMark1 = Gia_ObjIsXor(pObj) ? Value0 ^ Value1 : Value0 & Value1;
1188}
1189void Cec5_ManCexVerify( Gia_Man_t * p, int iObj0, int iObj1, int fPhase )
1190{
1191 int Value0, Value1;
1192 Gia_ManIncrementTravId( p );
1193 Value0 = Cec5_ManCexVerify_rec( p, iObj0 );
1194 Value1 = Cec5_ManCexVerify_rec( p, iObj1 );
1195 if ( (Value0 ^ Value1) == fPhase )
1196 printf( "CEX verification FAILED for obj %d and obj %d.\n", iObj0, iObj1 );
1197// else
1198// printf( "CEX verification succeeded for obj %d and obj %d.\n", iObj0, iObj1 );;
1199}
1200
1212void Cec5_ManPackAddPatterns( Gia_Man_t * p, int iBit, Vec_Int_t * vLits )
1213{
1214 int k, Limit = Abc_MinInt( Vec_IntSize(vLits), 64 * p->nSimWords - 1 );
1215 for ( k = 0; k < Limit; k++ )
1216 {
1217 int i, Lit, iBitLocal = (iBit + k + 1) % Limit + 1;
1218 assert( iBitLocal > 0 && iBitLocal < 64 * p->nSimWords );
1219 Vec_IntForEachEntry( vLits, Lit, i )
1220 {
1221 word * pInfo = Vec_WrdEntryP( p->vSims, p->nSimWords * Abc_Lit2Var(Lit) );
1222 word * pPres = Vec_WrdEntryP( p->vSimsPi, p->nSimWords * Abc_Lit2Var(Lit) );
1223 if ( Abc_InfoHasBit( (unsigned *)pPres, iBitLocal ) )
1224 continue;
1225 if ( Abc_InfoHasBit( (unsigned *)pInfo, iBitLocal ) != Abc_LitIsCompl(Lit ^ (i == k)) )
1226 Abc_InfoXorBit( (unsigned *)pInfo, iBitLocal );
1227 }
1228 }
1229}
1230int Cec5_ManPackAddPatternTry( Gia_Man_t * p, int iBit, Vec_Int_t * vLits )
1231{
1232 int i, Lit;
1233 assert( p->iPatsPi > 0 && p->iPatsPi < 64 * p->nSimWords );
1234 Vec_IntForEachEntry( vLits, Lit, i )
1235 {
1236 word * pInfo = Vec_WrdEntryP( p->vSims, p->nSimWords * Abc_Lit2Var(Lit) );
1237 word * pPres = Vec_WrdEntryP( p->vSimsPi, p->nSimWords * Abc_Lit2Var(Lit) );
1238 if ( Abc_InfoHasBit( (unsigned *)pPres, iBit ) &&
1239 Abc_InfoHasBit( (unsigned *)pInfo, iBit ) != Abc_LitIsCompl(Lit) )
1240 return 0;
1241 }
1242 Vec_IntForEachEntry( vLits, Lit, i )
1243 {
1244 word * pInfo = Vec_WrdEntryP( p->vSims, p->nSimWords * Abc_Lit2Var(Lit) );
1245 word * pPres = Vec_WrdEntryP( p->vSimsPi, p->nSimWords * Abc_Lit2Var(Lit) );
1246 Abc_InfoSetBit( (unsigned *)pPres, iBit );
1247 if ( Abc_InfoHasBit( (unsigned *)pInfo, iBit ) != Abc_LitIsCompl(Lit) )
1248 Abc_InfoXorBit( (unsigned *)pInfo, iBit );
1249 }
1250 return 1;
1251}
1252int Cec5_ManPackAddPattern( Gia_Man_t * p, Vec_Int_t * vLits, int fExtend )
1253{
1254 int k;
1255 for ( k = 1; k < 64 * p->nSimWords - 1; k++ )
1256 {
1257 if ( ++p->iPatsPi == 64 * p->nSimWords - 1 )
1258 p->iPatsPi = 1;
1259 if ( Cec5_ManPackAddPatternTry( p, p->iPatsPi, vLits ) )
1260 {
1261 if ( fExtend )
1262 Cec5_ManPackAddPatterns( p, p->iPatsPi, vLits );
1263 break;
1264 }
1265 }
1266 if ( k == 64 * p->nSimWords - 1 )
1267 {
1268 p->iPatsPi = k;
1269 if ( !Cec5_ManPackAddPatternTry( p, p->iPatsPi, vLits ) )
1270 printf( "Internal error.\n" );
1271 else if ( fExtend )
1272 Cec5_ManPackAddPatterns( p, p->iPatsPi, vLits );
1273 return 64 * p->nSimWords;
1274 }
1275 return k;
1276}
1277
1289static inline int Cec5_ObjFan0IsAssigned( Gia_Obj_t * pObj )
1290{
1291 return Gia_ObjFanin0(pObj)->fMark0 || Gia_ObjFanin0(pObj)->fMark1;
1292}
1293static inline int Cec5_ObjFan1IsAssigned( Gia_Obj_t * pObj )
1294{
1295 return Gia_ObjFanin1(pObj)->fMark0 || Gia_ObjFanin1(pObj)->fMark1;
1296}
1297static inline int Cec5_ObjFan0HasValue( Gia_Obj_t * pObj, int v )
1298{
1299 return (v ^ Gia_ObjFaninC0(pObj)) ? Gia_ObjFanin0(pObj)->fMark1 : Gia_ObjFanin0(pObj)->fMark0;
1300}
1301static inline int Cec5_ObjFan1HasValue( Gia_Obj_t * pObj, int v )
1302{
1303 return (v ^ Gia_ObjFaninC1(pObj)) ? Gia_ObjFanin1(pObj)->fMark1 : Gia_ObjFanin1(pObj)->fMark0;
1304}
1305static inline int Cec5_ObjObjIsImpliedValue( Gia_Obj_t * pObj, int v )
1306{
1307 assert( !pObj->fMark0 && !pObj->fMark1 ); // not visited
1308 if ( v )
1309 return Cec5_ObjFan0HasValue(pObj, 1) && Cec5_ObjFan1HasValue(pObj, 1);
1310 return Cec5_ObjFan0HasValue(pObj, 0) || Cec5_ObjFan1HasValue(pObj, 0);
1311}
1312static inline int Cec5_ObjFan0IsImpliedValue( Gia_Obj_t * pObj, int v )
1313{
1314 return Gia_ObjIsAnd(Gia_ObjFanin0(pObj)) && Cec5_ObjObjIsImpliedValue( Gia_ObjFanin0(pObj), v ^ Gia_ObjFaninC0(pObj) );
1315}
1316static inline int Cec5_ObjFan1IsImpliedValue( Gia_Obj_t * pObj, int v )
1317{
1318 return Gia_ObjIsAnd(Gia_ObjFanin1(pObj)) && Cec5_ObjObjIsImpliedValue( Gia_ObjFanin1(pObj), v ^ Gia_ObjFaninC1(pObj) );
1319}
1320int Cec5_ManGeneratePatterns_rec( Gia_Man_t * p, Gia_Obj_t * pObj, int Value, Vec_Int_t * vPat, Vec_Int_t * vVisit )
1321{
1322 Gia_Obj_t * pFan0, * pFan1;
1323 assert( !pObj->fMark0 && !pObj->fMark1 ); // not visited
1324 if ( Value ) pObj->fMark1 = 1; else pObj->fMark0 = 1;
1325 Vec_IntPush( vVisit, Gia_ObjId(p, pObj) );
1326 if ( Gia_ObjIsCi(pObj) )
1327 {
1328 Vec_IntPush( vPat, Abc_Var2Lit(Gia_ObjId(p, pObj), Value) );
1329 return 1;
1330 }
1331 assert( Gia_ObjIsAnd(pObj) );
1332 pFan0 = Gia_ObjFanin0(pObj);
1333 pFan1 = Gia_ObjFanin1(pObj);
1334 if ( Gia_ObjIsXor(pObj) )
1335 {
1336 int Ass0 = Cec5_ObjFan0IsAssigned(pObj);
1337 int Ass1 = Cec5_ObjFan1IsAssigned(pObj);
1338 assert( Gia_ObjFaninC0(pObj) == 0 && Gia_ObjFaninC1(pObj) == 0 );
1339 if ( Ass0 && Ass1 )
1340 return Value == (Cec5_ObjFan0HasValue(pObj, 1) ^ Cec5_ObjFan1HasValue(pObj, 1));
1341 if ( Ass0 )
1342 {
1343 int ValueInt = Value ^ Cec5_ObjFan0HasValue(pObj, 1);
1344 if ( !Cec5_ManGeneratePatterns_rec(p, pFan1, ValueInt, vPat, vVisit) )
1345 return 0;
1346 }
1347 else if ( Ass1 )
1348 {
1349 int ValueInt = Value ^ Cec5_ObjFan1HasValue(pObj, 1);
1350 if ( !Cec5_ManGeneratePatterns_rec(p, pFan0, ValueInt, vPat, vVisit) )
1351 return 0;
1352 }
1353 else if ( Abc_Random(0) & 1 )
1354 {
1355 if ( !Cec5_ManGeneratePatterns_rec(p, pFan0, 0, vPat, vVisit) )
1356 return 0;
1357 if ( Cec5_ObjFan1HasValue(pObj, !Value) || (!Cec5_ObjFan1HasValue(pObj, Value) && !Cec5_ManGeneratePatterns_rec(p, pFan1, Value, vPat, vVisit)) )
1358 return 0;
1359 }
1360 else
1361 {
1362 if ( !Cec5_ManGeneratePatterns_rec(p, pFan0, 1, vPat, vVisit) )
1363 return 0;
1364 if ( Cec5_ObjFan1HasValue(pObj, Value) || (!Cec5_ObjFan1HasValue(pObj, !Value) && !Cec5_ManGeneratePatterns_rec(p, pFan1, !Value, vPat, vVisit)) )
1365 return 0;
1366 }
1367 assert( Value == (Cec5_ObjFan0HasValue(pObj, 1) ^ Cec5_ObjFan1HasValue(pObj, 1)) );
1368 return 1;
1369 }
1370 else if ( Value )
1371 {
1372 if ( Cec5_ObjFan0HasValue(pObj, 0) || Cec5_ObjFan1HasValue(pObj, 0) )
1373 return 0;
1374 if ( !Cec5_ObjFan0HasValue(pObj, 1) && !Cec5_ManGeneratePatterns_rec(p, pFan0, !Gia_ObjFaninC0(pObj), vPat, vVisit) )
1375 return 0;
1376 if ( !Cec5_ObjFan1HasValue(pObj, 1) && !Cec5_ManGeneratePatterns_rec(p, pFan1, !Gia_ObjFaninC1(pObj), vPat, vVisit) )
1377 return 0;
1378 assert( Cec5_ObjFan0HasValue(pObj, 1) && Cec5_ObjFan1HasValue(pObj, 1) );
1379 return 1;
1380 }
1381 else
1382 {
1383 if ( Cec5_ObjFan0HasValue(pObj, 1) && Cec5_ObjFan1HasValue(pObj, 1) )
1384 return 0;
1385 if ( Cec5_ObjFan0HasValue(pObj, 0) || Cec5_ObjFan1HasValue(pObj, 0) )
1386 return 1;
1387 if ( Cec5_ObjFan0HasValue(pObj, 1) )
1388 {
1389 if ( !Cec5_ManGeneratePatterns_rec(p, pFan1, Gia_ObjFaninC1(pObj), vPat, vVisit) )
1390 return 0;
1391 }
1392 else if ( Cec5_ObjFan1HasValue(pObj, 1) )
1393 {
1394 if ( !Cec5_ManGeneratePatterns_rec(p, pFan0, Gia_ObjFaninC0(pObj), vPat, vVisit) )
1395 return 0;
1396 }
1397 else
1398 {
1399 if ( Cec5_ObjFan0IsImpliedValue( pObj, 0 ) )
1400 {
1401 if ( !Cec5_ManGeneratePatterns_rec(p, pFan0, Gia_ObjFaninC0(pObj), vPat, vVisit) )
1402 return 0;
1403 }
1404 else if ( Cec5_ObjFan1IsImpliedValue( pObj, 0 ) )
1405 {
1406 if ( !Cec5_ManGeneratePatterns_rec(p, pFan1, Gia_ObjFaninC1(pObj), vPat, vVisit) )
1407 return 0;
1408 }
1409 else if ( Cec5_ObjFan0IsImpliedValue( pObj, 1 ) )
1410 {
1411 if ( !Cec5_ManGeneratePatterns_rec(p, pFan1, Gia_ObjFaninC1(pObj), vPat, vVisit) )
1412 return 0;
1413 }
1414 else if ( Cec5_ObjFan1IsImpliedValue( pObj, 1 ) )
1415 {
1416 if ( !Cec5_ManGeneratePatterns_rec(p, pFan0, Gia_ObjFaninC0(pObj), vPat, vVisit) )
1417 return 0;
1418 }
1419 else if ( Abc_Random(0) & 1 )
1420 {
1421 if ( !Cec5_ManGeneratePatterns_rec(p, pFan1, Gia_ObjFaninC1(pObj), vPat, vVisit) )
1422 return 0;
1423 }
1424 else
1425 {
1426 if ( !Cec5_ManGeneratePatterns_rec(p, pFan0, Gia_ObjFaninC0(pObj), vPat, vVisit) )
1427 return 0;
1428 }
1429 }
1430 assert( Cec5_ObjFan0HasValue(pObj, 0) || Cec5_ObjFan1HasValue(pObj, 0) );
1431 return 1;
1432 }
1433}
1434int Cec5_ManGeneratePatternOne( Gia_Man_t * p, int iRepr, int iReprVal, int iCand, int iCandVal, Vec_Int_t * vPat, Vec_Int_t * vVisit )
1435{
1436 int Res, k;
1437 Gia_Obj_t * pObj;
1438 assert( iCand > 0 );
1439 if ( !iRepr && iReprVal )
1440 return 0;
1441 Vec_IntClear( vPat );
1442 Vec_IntClear( vVisit );
1443 //Gia_ManForEachObj( p, pObj, k )
1444 // assert( !pObj->fMark0 && !pObj->fMark1 );
1445 Res = (!iRepr || Cec5_ManGeneratePatterns_rec(p, Gia_ManObj(p, iRepr), iReprVal, vPat, vVisit)) && Cec5_ManGeneratePatterns_rec(p, Gia_ManObj(p, iCand), iCandVal, vPat, vVisit);
1446 Gia_ManForEachObjVec( vVisit, p, pObj, k )
1447 pObj->fMark0 = pObj->fMark1 = 0;
1448 return Res;
1449}
1450void Cec5_ManCandIterStart( Cec5_Man_t * p )
1451{
1452 int i, * pArray;
1453 assert( p->iPosWrite == 0 );
1454 assert( p->iPosRead == 0 );
1455 assert( Vec_IntSize(p->vCands) == 0 );
1456 for ( i = 1; i < Gia_ManObjNum(p->pAig); i++ )
1457 if ( Gia_ObjRepr(p->pAig, i) != GIA_VOID )
1458 Vec_IntPush( p->vCands, i );
1459 pArray = Vec_IntArray( p->vCands );
1460 for ( i = 0; i < Vec_IntSize(p->vCands); i++ )
1461 {
1462 int iNew = Abc_Random(0) % Vec_IntSize(p->vCands);
1463 ABC_SWAP( int, pArray[i], pArray[iNew] );
1464 }
1465}
1466int Cec5_ManCandIterNext( Cec5_Man_t * p )
1467{
1468 while ( Vec_IntSize(p->vCands) > 0 )
1469 {
1470 int fStop, iCand = Vec_IntEntry( p->vCands, p->iPosRead );
1471 if ( (fStop = (Gia_ObjRepr(p->pAig, iCand) != GIA_VOID)) )
1472 Vec_IntWriteEntry( p->vCands, p->iPosWrite++, iCand );
1473 if ( ++p->iPosRead == Vec_IntSize(p->vCands) )
1474 {
1475 Vec_IntShrink( p->vCands, p->iPosWrite );
1476 p->iPosWrite = 0;
1477 p->iPosRead = 0;
1478 }
1479 if ( fStop )
1480 return iCand;
1481 }
1482 return 0;
1483}
1484int Cec5_ManGeneratePatterns( Cec5_Man_t * p )
1485{
1486 abctime clk = Abc_Clock();
1487 int i, iCand, nPats = 100 * 64 * p->pAig->nSimWords, CountPat = 0, Packs = 0;
1488 //int iRepr;
1489 //Vec_IntForEachEntryDouble( p->vDisprPairs, iRepr, iCand, i )
1490 // if ( iRepr == Gia_ObjRepr(p->pAig, iCand) )
1491 // printf( "Pair %6d (%6d, %6d) (new repr = %9d) is FAILED to disprove.\n", i, iRepr, iCand, Gia_ObjRepr(p->pAig, iCand) );
1492 // else
1493 // printf( "Pair %6d (%6d, %6d) (new repr = %9d) is disproved.\n", i, iRepr, iCand, Gia_ObjRepr(p->pAig, iCand) );
1494 //Vec_IntClear( p->vDisprPairs );
1495 p->pAig->iPatsPi = 0;
1496 Vec_WrdFill( p->pAig->vSimsPi, Vec_WrdSize(p->pAig->vSimsPi), 0 );
1497 for ( i = 0; i < nPats; i++ )
1498 if ( (iCand = Cec5_ManCandIterNext(p)) )
1499 {
1500 int iRepr = Gia_ObjRepr( p->pAig, iCand );
1501 int iCandVal = Gia_ManObj(p->pAig, iCand)->fPhase;
1502 int iReprVal = Gia_ManObj(p->pAig, iRepr)->fPhase;
1503 int Res = Cec5_ManGeneratePatternOne( p->pAig, iRepr, iReprVal, iCand, !iCandVal, p->vPat, p->vVisit );
1504 if ( !Res )
1505 Res = Cec5_ManGeneratePatternOne( p->pAig, iRepr, !iReprVal, iCand, iCandVal, p->vPat, p->vVisit );
1506 if ( Res )
1507 {
1508 int Ret = Cec5_ManPackAddPattern( p->pAig, p->vPat, 1 );
1509 if ( p->pAig->vPats )
1510 {
1511 Vec_IntPush( p->pAig->vPats, Vec_IntSize(p->vPat)+2 );
1512 Vec_IntAppend( p->pAig->vPats, p->vPat );
1513 Vec_IntPush( p->pAig->vPats, -1 );
1514 }
1515 //Vec_IntPushTwo( p->vDisprPairs, iRepr, iCand );
1516 Packs += Ret;
1517 if ( 0 == (Ret % (64 * p->pAig->nSimWords / p->simBatchFactor)) )
1518 break;
1519 if ( ++CountPat == 8 * 64 * p->pAig->nSimWords )
1520 break;
1521 //Cec5_ManCexVerify( p->pAig, iRepr, iCand, iReprVal ^ iCandVal );
1522 //Gia_ManCleanMark01( p->pAig );
1523 }
1524 }
1525 p->timeGenPats += Abc_Clock() - clk;
1526 p->nSatSat += CountPat;
1527 //printf( "%3d : %6.2f %% : Generated %6d CEXs after trying %6d pairs. Ave packs = %9.2f Ave tries = %9.2f (Limit = %9.2f)\n",
1528 // p->nItersSim++, 100.0*Vec_IntSize(p->vCands)/Gia_ManAndNum(p->pAig),
1529 // CountPat, i, (float)Packs / Abc_MaxInt(1, CountPat), (float)i / Abc_MaxInt(1, CountPat), (float)nPats / p->pPars->nItersMax );
1530 return CountPat >= i / p->pPars->nItersMax;
1531}
1532
1533
1545void Cec5_ManSatSolverRecycle( Cec5_Man_t * p )
1546{
1547 Gia_Obj_t * pObj;
1548 int i;
1549 //printf( "Solver size = %d.\n", sat_solver_varnum(p->pSat) );
1550 if( p->adaRecycle && p->adaRecycle < p->nConflicts[2][2] )
1551 return;
1552 p->nRecycles++;
1553 p->nCallsSince = 0;
1554 sat_solver_reset( p->pSat );
1555 // clean mapping of AigIds into SatIds
1556 Gia_ManForEachObjVec( &p->pNew->vSuppVars, p->pNew, pObj, i )
1557 Cec5_ObjCleanSatId( p->pNew, pObj );
1558 Vec_IntClear( &p->pNew->vSuppVars ); // AigIds for which SatId is defined
1559 Vec_IntClear( &p->pNew->vCopiesTwo ); // pairs (CiAigId, SatId)
1560 Vec_IntClear( &p->pNew->vVarMap ); // mapping of SatId into AigId
1561}
1562void Cec5_ManLoadInstance( Cec5_Man_t * p, int iObj0, int iObj1, int * piVar0, int * piVar1 ){
1563 int iVar0 = Cec5_ObjGetCnfVar( p, iObj0 );
1564 int iVar1 = Cec5_ObjGetCnfVar( p, iObj1 );
1565 if( p->pPars->jType > 0 )
1566 {
1567 int nlim = p->approxLim;
1568 bmcg2_sat_solver_markapprox( p->pSat, iVar0, iVar1, nlim );
1569 }
1570
1571 * piVar0 = iVar0;
1572 * piVar1 = iVar1;
1573}
1574
1575int Cec5_ManSolveTwo( Cec5_Man_t * p, int iObj0, int iObj1, int fPhase, int * pfEasy, int fVerbose, int fEffort )
1576{
1577 abctime clk;
1578 int nBTLimit = fEffort ? p->pPars->nBTLimitPo : (Vec_BitEntry(p->vFails, iObj0) || Vec_BitEntry(p->vFails, iObj1)) ? Abc_MaxInt(1, p->pPars->nBTLimit/10) : p->pPars->nBTLimit;
1579 int nConfEnd, nConfBeg, status, iVar0, iVar1, Lits[2];
1580 int UnsatConflicts[3] = {0};
1581 //printf( "%d ", nBTLimit );
1582 if ( iObj1 < iObj0 )
1583 iObj1 ^= iObj0, iObj0 ^= iObj1, iObj1 ^= iObj0;
1584 assert( iObj0 < iObj1 );
1585 *pfEasy = 0;
1586 // check if SAT solver needs recycling
1587 p->nCallsSince++;
1588 if ( p->nCallsSince > p->pPars->nCallsRecycle &&
1589 Vec_IntSize(&p->pNew->vSuppVars) > p->pPars->nSatVarMax && p->pPars->nSatVarMax )
1590 Cec5_ManSatSolverRecycle( p );
1591 // add more logic to the solver
1592 if ( !iObj0 && Cec5_ObjSatId(p->pNew, Gia_ManConst0(p->pNew)) == -1 )
1593 Cec5_ObjSetSatId( p->pNew, Gia_ManConst0(p->pNew), sat_solver_addvar(p->pSat) );
1594 clk = Abc_Clock();
1595 Cec5_ManLoadInstance( p, iObj0, iObj1, &iVar0, &iVar1);
1596 p->timeCnf += Abc_Clock() - clk;
1597 // perform solving
1598 Lits[0] = Abc_Var2Lit(iVar0, 1);
1599 Lits[1] = Abc_Var2Lit(iVar1, fPhase);
1600 sat_solver_set_conflict_budget( p->pSat, nBTLimit );
1601 nConfBeg = sat_solver_conflictnum( p->pSat );
1602 status = sat_solver_solve( p->pSat, Lits, 2 );
1603 nConfEnd = sat_solver_conflictnum( p->pSat );
1604 assert( nConfEnd >= nConfBeg );
1605 p->nConflicts[2][2] = Abc_MaxInt(p->nConflicts[2][2], nConfEnd - nConfBeg);
1606 if ( fVerbose )
1607 {
1608 if ( status == GLUCOSE_SAT )
1609 {
1610 p->nConflicts[0][0] += nConfEnd == nConfBeg;
1611 p->nConflicts[0][1] += nConfEnd - nConfBeg;
1612 p->nConflicts[0][2] = Abc_MaxInt(p->nConflicts[0][2], nConfEnd - nConfBeg);
1613 *pfEasy = nConfEnd == nConfBeg;
1614 }
1615 else if ( status == GLUCOSE_UNSAT )
1616 {
1617 if ( iObj0 > 0 )
1618 {
1619 UnsatConflicts[0] = nConfEnd == nConfBeg;
1620 UnsatConflicts[1] = nConfEnd - nConfBeg;
1621 UnsatConflicts[2] = Abc_MaxInt(p->nConflicts[1][2], nConfEnd - nConfBeg);
1622 p->nConflicts[1][2] = Abc_MaxInt(p->nConflicts[1][2], UnsatConflicts[2]);
1623 }
1624 else
1625 {
1626 p->nConflicts[1][0] += nConfEnd == nConfBeg;
1627 p->nConflicts[1][1] += nConfEnd - nConfBeg;
1628 p->nConflicts[1][2] = Abc_MaxInt(p->nConflicts[1][2], nConfEnd - nConfBeg);
1629 *pfEasy = nConfEnd == nConfBeg;
1630 }
1631 }
1632 }
1633 if ( status == GLUCOSE_UNSAT && iObj0 > 0 )
1634 {
1635 Lits[0] = Abc_Var2Lit(iVar0, 0);
1636 Lits[1] = Abc_Var2Lit(iVar1, !fPhase);
1637 sat_solver_set_conflict_budget( p->pSat, nBTLimit );
1638 nConfBeg = sat_solver_conflictnum( p->pSat );
1639 status = sat_solver_solve( p->pSat, Lits, 2 );
1640 nConfEnd = sat_solver_conflictnum( p->pSat );
1641 assert( nConfEnd >= nConfBeg );
1642 p->nConflicts[2][2] = Abc_MaxInt(p->nConflicts[2][2], nConfEnd - nConfBeg);
1643 if ( fVerbose )
1644 {
1645 if ( status == GLUCOSE_SAT )
1646 {
1647 p->nConflicts[0][0] += nConfEnd == nConfBeg;
1648 p->nConflicts[0][1] += nConfEnd - nConfBeg;
1649 p->nConflicts[0][2] = Abc_MaxInt(p->nConflicts[0][2], nConfEnd - nConfBeg);
1650 *pfEasy = nConfEnd == nConfBeg;
1651 }
1652 else if ( status == GLUCOSE_UNSAT )
1653 {
1654 UnsatConflicts[0] &= nConfEnd == nConfBeg;
1655 UnsatConflicts[1] += nConfEnd - nConfBeg;
1656 UnsatConflicts[2] = Abc_MaxInt(p->nConflicts[1][2], nConfEnd - nConfBeg);
1657
1658 p->nConflicts[1][0] += UnsatConflicts[0];
1659 p->nConflicts[1][1] += UnsatConflicts[1];
1660 p->nConflicts[1][2] = Abc_MaxInt(p->nConflicts[1][2], UnsatConflicts[2]);
1661 *pfEasy = UnsatConflicts[0];
1662 }
1663 }
1664 }
1665 //if ( status == GLUCOSE_UNDEC )
1666 // printf( "* " );
1667 return status;
1668}
1669void Cec5_FlushCache2Pattern( Cec5_Man_t * p ){
1670 int j, iLit, nWrite = 0;
1671 int iPatsOld = p->pAig->iPatsPi;
1672 j = 0;
1673 p->pAig->iPatsPi -- ;
1674 while( j < p->vPiPatsCache->nSize ){
1675 if( -1 < (iLit = p->vPiPatsCache->pArray[j++]) ){
1676 Cec5_ObjSimSetInputBit( p->pAig, Abc_Lit2Var(iLit), Abc_LitIsCompl(iLit) );
1677 continue;
1678 }
1679 p->pAig->iPatsPi -- ;
1680 nWrite ++ ;
1681 }
1682 p->pAig->iPatsPi += nWrite+1;
1683 assert( iPatsOld == p->pAig->iPatsPi );
1684 p->vPiPatsCache->nSize = 0;
1685}
1686void Cec5_ClearCexMarks( Cec5_Man_t * p ){
1687 Vec_IntFill( p->vCexStamps, Gia_ManObjNum(p->pAig), 0 );
1688 Vec_BitFill( p->vCexSite , Gia_ManObjNum(p->pAig), 0 );
1689}
1690void Cec5_ManCheckGlobalSim( Cec5_Man_t * p){
1691 int iPatTop = p->pAig->iPatsPi;
1692 if ( (iPatTop % (sizeof(word) * 8 * p->pAig->nSimWords / p->simBatchFactor)) == 0
1693 || iPatTop == (int)sizeof(word) * 8 * p->pAig->nSimWords - 2 )
1694 {
1695 abctime clk2 = Abc_Clock();
1696 Cec5_FlushCache2Pattern(p);
1697 //p->simBound = iPatTop / (sizeof(word) * 8 * p->pAig->nSimWords / p->simBatchFactor)+2;//p->simTravId * p->LocalBatchSize / (sizeof(word) * 8<<3)+1;
1698 p->simBound = iPatTop / (sizeof(word) * 8) + ((iPatTop % (sizeof(word) * 8)) ? 1: 0);
1699 //if( iPatTop == sizeof(word) * 8 * p->pAig->nSimWords - 2 )
1700 // p->simBound += 1;
1701 //printf("re-sim %5d %5d bound %5d\n", p->pAig->iPatsPi, p->simTravId, p->simBound );
1702 Cec5_ManSimulate( p->pAig, p );
1703 p->simBound = p->pPars->nWords;
1704 //printf( "FasterSmall = %d. FasterBig = %d.\n", p->nFaster[0], p->nFaster[1] );
1705 p->nFaster[0] = p->nFaster[1] = 0;
1706 //if ( p->nSatSat && p->nSatSat % 100 == 0 )
1707 //Cec5_ManPrintStats( p->pAig, p->pPars, p, 0 );
1708 Cec5_ClearCexMarks(p);
1709 if( iPatTop == (int)sizeof(word) * 8 * p->pAig->nSimWords - 2 ){
1710 Cec5_ManPrintStats( p->pAig, p->pPars, p, 0 );
1711 p->pAig->iPatsPi = 0;
1712 p->simTravId = 0;
1713 p->simGlobalTop = 0;
1714 } else {
1715 //assert( 0 == iPatTop % (sizeof(word) * 8 * p->pAig->nSimWords) );
1716 p->pAig->iPatsPi = iPatTop;
1717 p->simGlobalTop = iPatTop / (sizeof(word) * 8 );
1718 }
1719 Vec_WrdFill( p->pAig->vSimsPi, Vec_WrdSize(p->pAig->vSimsPi), 0 );
1720 p->timeResimGlo += Abc_Clock() - clk2;
1721 }
1722}
1723int Cec5_ManSweepNode( Cec5_Man_t * p, int iObj, int iRepr )
1724{
1725 abctime clk = Abc_Clock();
1726 int i, IdAig, IdSat, status, fEasy, RetValue = 1;
1727 Gia_Obj_t * pObj = Gia_ManObj( p->pAig, iObj );
1728 Gia_Obj_t * pRepr = Gia_ManObj( p->pAig, iRepr );
1729 int fCompl = Abc_LitIsCompl(pObj->Value) ^ Abc_LitIsCompl(pRepr->Value) ^ pObj->fPhase ^ pRepr->fPhase;
1730 int fEffort = p->vCoDrivers ? Vec_BitEntry(p->vCoDrivers, iObj) || Vec_BitEntry(p->vCoDrivers, iRepr) : 0;
1731 status = Cec5_ManSolveTwo( p, Abc_Lit2Var(pRepr->Value), Abc_Lit2Var(pObj->Value), fCompl, &fEasy, p->pPars->fVerbose, fEffort );
1732 if ( status == GLUCOSE_SAT )
1733 {
1734 int iLit;
1735 Vec_BitWriteEntry( p->vCexSite, iObj, 1 );
1736 //int iPatsOld = p->pAig->iPatsPi;
1737 //printf( "Disproved: %d == %d.\n", Abc_Lit2Var(pRepr->Value), Abc_Lit2Var(pObj->Value) );
1738 p->nSatSat++;
1739 p->nPatterns++;
1740 Vec_IntClear( p->vPat );
1741 if ( p->pPars->jType == 0 )
1742 {
1743 Vec_IntForEachEntryDouble( &p->pNew->vCopiesTwo, IdAig, IdSat, i )
1744 Vec_IntPush( p->vPat, Abc_Var2Lit(IdAig, sat_solver_read_cex_varvalue(p->pSat, IdSat)) );
1745 }
1746 else
1747 {
1748 int * pCex = sat_solver_read_cex( p->pSat );
1749 int * pMap = Vec_IntArray(&p->pNew->vVarMap);
1750 for ( i = 0; i < pCex[0]; )
1751 Vec_IntPush( p->vPat, Abc_Lit2LitV(pMap, Abc_LitNot(pCex[++i])) );
1752 }
1753 assert( p->pAig->iPatsPi >= 0 && p->pAig->iPatsPi < 64 * p->pAig->nSimWords - 1 );
1754 p->pAig->iPatsPi++;
1755// Vec_IntForEachEntry( p->vPat, iLit, i )
1756// Cec5_ObjSimSetInputBit( p->pAig, Abc_Lit2Var(iLit), Abc_LitIsCompl(iLit) );
1757 Vec_IntForEachEntry( p->vPat, iLit, i )
1758 Vec_IntPush( p->vPiPatsCache, iLit );
1759 Vec_IntPush( p->vPiPatsCache, -1 );
1760 if ( p->pAig->vPats )
1761 {
1762 Vec_IntPush( p->pAig->vPats, Vec_IntSize(p->vPat)+2 );
1763 Vec_IntAppend( p->pAig->vPats, p->vPat );
1764 Vec_IntPush( p->pAig->vPats, -1 );
1765 }
1766 //Cec5_ManPackAddPattern( p->pAig, p->vPat, 0 );
1767 //assert( iPatsOld + 1 == p->pAig->iPatsPi );
1768 if ( fEasy )
1769 p->timeSatSat0 += Abc_Clock() - clk;
1770 else
1771 p->timeSatSat += Abc_Clock() - clk;
1772 RetValue = 0;
1773
1774 p->simTravId = p->pAig->iPatsPi / p->LocalBatchSize;
1775 if( (p->pAig->iPatsPi % p->LocalBatchSize) == 0 || 1 == p->LocalBatchSize )
1776 Cec5_FlushCache2Pattern(p);
1777
1778 // this is not needed, but we keep it here anyway, because it takes very little time
1779 //Cec5_ManVerify( p->pNew, Abc_Lit2Var(pRepr->Value), Abc_Lit2Var(pObj->Value), fCompl, p->pSat );
1780 // resimulated once in a while
1781 //if ( p->pAig->iPatsPi == 64 * p->pAig->nSimWords - 2 )
1782 Cec5_ManCheckGlobalSim(p);
1783 }
1784 else if ( status == GLUCOSE_UNSAT )
1785 {
1786 //printf( "Proved: %d == %d.\n", Abc_Lit2Var(pRepr->Value), Abc_Lit2Var(pObj->Value) );
1787 p->nSatUnsat++;
1788 pObj->Value = Abc_LitNotCond( pRepr->Value, fCompl );
1789 assert( !Gia_ObjProved( p->pAig, iObj ) );
1790 Gia_ObjSetProved( p->pAig, iObj );
1791 if ( iRepr == 0 )
1792 p->iLastConst = iObj;
1793 if ( fEasy )
1794 p->timeSatUnsat0 += Abc_Clock() - clk;
1795 else
1796 p->timeSatUnsat += Abc_Clock() - clk;
1797 RetValue = 1;
1798 }
1799 else
1800 {
1801 p->nSatUndec++;
1802 assert( status == GLUCOSE_UNDEC );
1803 Gia_ObjSetFailed( p->pAig, iObj );
1804 Vec_BitWriteEntry( p->vFails, iObj, 1 );
1805 //if ( iRepr )
1806 //Vec_BitWriteEntry( p->vFails, iRepr, 1 );
1807 p->timeSatUndec += Abc_Clock() - clk;
1808 RetValue = 2;
1809 }
1810 return RetValue;
1811}
1812Gia_Obj_t * Cec5_ManFindRepr( Gia_Man_t * p, Cec5_Man_t * pMan, int iObj )
1813{
1814 abctime clk = Abc_Clock();
1815 Gia_Obj_t * pRepr = NULL;
1816 int iMem, iRepr;
1817 assert( Gia_ObjHasRepr(p, iObj) );
1818 assert( !Gia_ObjProved(p, iObj) );
1819 iRepr = Gia_ObjRepr(p, iObj);
1820 assert( iRepr != iObj );
1821 assert( !Gia_ObjProved(p, iRepr) );
1822
1823 pMan->simBound = pMan->simTravId * pMan->LocalBatchSize / (sizeof(word)<<3)+1;
1824 assert( pMan->simBound <= pMan->pPars->nWords );
1825
1826 if( (Vec_BitEntry( pMan->vCexSite, iObj ) | Vec_BitEntry( pMan->vCexSite, iRepr ))
1827 ||(Vec_IntEntry( pMan->vCexStamps, iObj ) != Vec_IntEntry( pMan->vCexStamps, iRepr )) ){
1828 Cec5_ManSimulate_rec( p, pMan, iObj );
1829 Cec5_ManSimulate_rec( p, pMan, iRepr );
1830 }
1831 if ( Cec5_ObjSimEqual(p, iObj, iRepr) )
1832 {
1833 pMan->timeResimLoc += Abc_Clock() - clk;
1834 pRepr = Gia_ManObj(p, iRepr);
1835 goto finalize;
1836 }
1837 Gia_ClassForEachObj1( p, iRepr, iMem )
1838 {
1839 if ( iObj == iMem )
1840 break;
1841 assert(iMem<iObj);
1842 if ( Gia_ObjProved(p, iMem) || Gia_ObjFailed(p, iMem) )
1843 continue;
1844 if( Vec_IntEntry( pMan->vCexStamps, iObj ) != Vec_IntEntry( pMan->vCexStamps, iMem ) ){
1845 Cec5_ManSimulate_rec( p, pMan, iMem );
1846 Cec5_ManSimulate_rec( p, pMan, iObj );
1847 }
1848 if ( Cec5_ObjSimEqual(p, iObj, iMem) )
1849 {
1850 pMan->nFaster[0]++;
1851 pMan->timeResimLoc += Abc_Clock() - clk;
1852 pRepr = Gia_ManObj(p, iMem);
1853 goto finalize;
1854 }
1855 }
1856 pMan->nFaster[1]++;
1857 pMan->timeResimLoc += Abc_Clock() - clk;
1858finalize:
1859 pMan->simBound = pMan->pPars->nWords;
1860 return pRepr;
1861}
1862void Cec5_ManExtend( Cec5_Man_t * pMan, CbsP_Man_t * pCbs ){
1863 while( pMan->pNew->vCopies2.nSize < Gia_ManObjNum(pMan->pNew) ){
1864 Vec_IntPush( &pMan->pNew->vCopies2, -1 );
1865 Vec_BitPush( pMan->vFails, 0 );
1866 if( pCbs )
1867 Vec_IntPush( pCbs->vValue, ~0 );
1868 }
1869}
1870
1871int Cec5_ManSweepNodeCbs( Cec5_Man_t * p, CbsP_Man_t * pCbs, int iObj, int iRepr, int fTagFail );
1872int Cec5_ManPerformSweeping( Gia_Man_t * p, Cec_ParFra_t * pPars, Gia_Man_t ** ppNew, int fSimOnly, int fCbs, int approxLim, int subBatchSz, int adaRecycle )
1873{
1874 extern void Gia_ManRemoveWrongChoices( Gia_Man_t * p );
1875 Gia_Obj_t * pObj, * pRepr;
1876 CbsP_Man_t * pCbs = NULL;
1877 int i, fSimulate = 1;
1878 int fPrep = 0;
1879 int AccuSat = 0;
1880 int * vMerged;
1881 int go_back = -1;
1882
1883 Cec5_Man_t * pMan = Cec5_ManCreate( p, pPars );
1884 pMan->approxLim = approxLim;
1885 if( pMan->simBatchFactor != subBatchSz ){
1886 printf("overwrite default batch size: from %3d to %3d\n", pMan->simBatchFactor, subBatchSz);
1887 pMan->simBatchFactor = subBatchSz;
1888 }
1889 if( pMan->adaRecycle != adaRecycle ){
1890 printf("overwrite default adaptive recycle: from %3d to %3d\n", pMan->adaRecycle, adaRecycle);
1891 pMan->adaRecycle = adaRecycle;
1892 }
1893 if ( pPars->fVerbose )
1894 printf( "Solver type = %d. Simulate %d words in %d rounds. SAT with %d confs. Recycle after %d SAT calls.\n",
1895 pPars->jType, pPars->nWords, pPars->nRounds, pPars->nBTLimit, pPars->nCallsRecycle );
1896
1897 if( fPrep )
1898 pMan->fEec = 1;
1899
1900
1901 // this is currently needed to have a correct mapping
1902 Gia_ManForEachCi( p, pObj, i )
1903 assert( Gia_ObjId(p, pObj) == i+1 );
1904
1905 // check if any output trivially fails under all-0 pattern
1906 Abc_Random( 1 );
1907 Gia_ManSetPhase( p );
1908 if ( pPars->nLevelMax )
1909 Gia_ManLevelNum(p);
1910 //Gia_ManStaticFanoutStart( p );
1911 if ( pPars->fCheckMiter )
1912 {
1913 Gia_ManForEachCo( p, pObj, i )
1914 if ( pObj->fPhase )
1915 {
1916 p->pCexSeq = Cec5_ManDeriveCex( p, i, -1 );
1917 goto finalize;
1918 }
1919 }
1920
1921 // simulate one round and create classes
1922 Cec5_ManSimAlloc( p, pPars->nWords, 0 );
1923 Cec5_ManSimulateCis( p );
1924 Cec5_ManSimulate( p, pMan );
1925 if ( pPars->fCheckMiter && !Cec5_ManSimulateCos(p) ) // cex detected
1926 goto finalize;
1927 if ( pPars->fVerbose )
1928 Cec5_ManPrintStats( p, pPars, pMan, 1 );
1929
1930 // perform simulation
1931 for ( i = 0; i < pPars->nRounds; i++ )
1932 {
1933 Cec5_ManSimulateCis( p );
1934 Cec5_ManSimulate( p, pMan );
1935 if ( pPars->fCheckMiter && !Cec5_ManSimulateCos(p) ) // cex detected
1936 goto finalize;
1937 if ( i && i % (pPars->nRounds / 5) == 0 && pPars->fVerbose )
1938 Cec5_ManPrintStats( p, pPars, pMan, 1 );
1939 }
1940 if ( fSimOnly )
1941 goto finalize;
1942
1943
1944 // perform additional simulation
1945 Cec5_ManCandIterStart( pMan );
1946 for ( i = 0; fSimulate && i < pPars->nGenIters; i++ )
1947 {
1948 Cec5_ManSimulateCis( p );
1949 fSimulate = Cec5_ManGeneratePatterns( pMan );
1950 Cec5_ManSimulate( p, pMan );
1951 if ( pPars->fCheckMiter && !Cec5_ManSimulateCos(p) ) // cex detected
1952 goto finalize;
1953 if ( i && i % 5 == 0 && pPars->fVerbose )
1954 Cec5_ManPrintStats( p, pPars, pMan, 1 );
1955 if( pMan->nSatSat - AccuSat < p->nSimWords * (int)sizeof(word) * 8 )
1956 break;
1957
1958 AccuSat = pMan->nSatSat;
1959 }
1960 if ( i && i % 5 && pPars->fVerbose )
1961 Cec5_ManPrintStats( p, pPars, pMan, 1 );
1962
1963 vMerged = ABC_FALLOC(int, Gia_ManObjNum(p)); // refinement may move non-repr merge around . record the true merged performed
1964
1965 p->iPatsPi = 0;
1966 Vec_WrdFill( p->vSimsPi, Vec_WrdSize(p->vSimsPi), 0 );
1967 pMan->nSatSat = 0;
1968 pMan->pNew = Cec5_ManStartNew( p );
1969
1970 if( fCbs ){
1971 //Gia_ManCreateRefs( pMan->pNew );
1972 pMan->pNew->pRefs = ABC_CALLOC( int, Gia_ManObjNum(p) );
1973 Gia_ManCleanMark0( pMan->pNew );
1974 Gia_ManCleanMark1( pMan->pNew );
1975 Gia_ManFillValue ( pMan->pNew );
1976 pCbs = CbsP_ManAlloc( p );
1977 pCbs->pAig = pMan->pNew;
1978 pCbs->Pars.nBTLimit = 100;//pPars->nBTLimit;
1979 pCbs->Pars.nJustLimit = 100;
1980 pCbs->Pars.nJscanLimit = 100;
1981 pCbs->Pars.nRscanLimit = 100;
1982 pCbs->Pars.nPropLimit = 100;
1983
1984 if( pPars->fVerbose ){
1985 printf("cbs: clim = %4d jlim = %4d\n"
1986 , pCbs->Pars.nBTLimit
1987 , pCbs->Pars.nJustLimit );
1988 }
1989 }
1990
1991 //Gia_ManForEachAnd( p, pObj, i )
1992 i = 0;
1993resume:
1994 for( ; i < Gia_ManObjNum(p) && (pObj = Gia_ManObj(p,i)); i ++ )
1995 {
1996 int status = 2;
1997 Gia_Obj_t * pObjNew;
1998 if ( !Gia_ObjIsAnd(pObj) )
1999 continue;
2000
2001 Vec_BitWriteEntry( pMan->vCexSite, i
2002 , Vec_BitEntry( pMan->vCexSite, Gia_ObjFaninId0(pObj,i) )
2003 | Vec_BitEntry( pMan->vCexSite, Gia_ObjFaninId1(pObj,i) ) );
2004
2005 if ( Gia_ObjFailed(p,i) )
2006 continue;
2007 pMan->nAndNodes++;
2008 if ( Gia_ObjProved(p, i) ){
2009 pRepr = Gia_ManObj( p, vMerged[i] );
2010 pObj->Value = Abc_LitNotCond( pRepr->Value, pObj->fPhase ^ pRepr->fPhase ); // upate in case repr rehashed due to fanin its backtrace
2011 continue;
2012 }
2013
2014 if ( Gia_ObjIsXor(pObj) )
2015 pObj->Value = Gia_ManHashXorReal( pMan->pNew, Gia_ObjFanin0Copy(pObj), Gia_ObjFanin1Copy(pObj) );
2016 else
2017 pObj->Value = Gia_ManHashAnd( pMan->pNew, Gia_ObjFanin0Copy(pObj), Gia_ObjFanin1Copy(pObj) );
2018
2019 Cec5_ManExtend( pMan, pCbs );
2020
2021 if ( pPars->nLevelMax && Gia_ObjLevel(p, pObj) > pPars->nLevelMax )
2022 continue;
2023
2024 pObjNew = Gia_ManObj( pMan->pNew, Abc_Lit2Var(pObj->Value) );
2025 if ( Gia_ObjIsAnd(pObjNew) )
2026 if ( Vec_BitEntry(pMan->vFails, Gia_ObjFaninId0(pObjNew, Abc_Lit2Var(pObj->Value))) ||
2027 Vec_BitEntry(pMan->vFails, Gia_ObjFaninId1(pObjNew, Abc_Lit2Var(pObj->Value))) )
2028 Vec_BitWriteEntry( pMan->vFails, Abc_Lit2Var(pObjNew->Value), 1 );
2029 //if ( Gia_ObjIsAnd(pObjNew) )
2030 // Gia_ObjSetAndLevel( pMan->pNew, pObjNew );
2031 // select representative based on candidate equivalence classes
2032 pRepr = Gia_ObjReprObj( p, i );
2033
2034 if ( pRepr == NULL )
2035 continue;
2036
2037 if ( 1 ) // select representative based on recent counter-examples
2038 {
2039 pRepr = Cec5_ManFindRepr( p, pMan, i );
2040 if ( pRepr == NULL )
2041 continue;
2042 }
2043 if ( Abc_Lit2Var(pObj->Value) == Abc_Lit2Var(pRepr->Value) )
2044 {
2045 assert( (pObj->Value ^ pRepr->Value) == (pObj->fPhase ^ pRepr->fPhase) );
2046 vMerged[i] = Gia_ObjId(p, pRepr);
2047 Gia_ObjSetProved( p, i );
2048 if ( Gia_ObjId(p, pRepr) == 0 )
2049 pMan->iLastConst = i;
2050
2051 continue;
2052 }
2053
2054 if ( fCbs && (status = Cec5_ManSweepNodeCbs(pMan, pCbs, i, Gia_ObjId(p, pRepr), 0)) && Gia_ObjProved(p, i) ){
2055 vMerged[i] = Gia_ObjId(p, pRepr);
2056 pObj->Value = Abc_LitNotCond( pRepr->Value, pObj->fPhase ^ pRepr->fPhase );
2057 }
2058
2059 if ( 2 == status && (status = Cec5_ManSweepNode(pMan, i, Gia_ObjId(p, pRepr))) && Gia_ObjProved(p, i) ){
2060 vMerged[i] = Gia_ObjId(p, pRepr);
2061 pObj->Value = Abc_LitNotCond( pRepr->Value, pObj->fPhase ^ pRepr->fPhase );
2062 }
2063
2064 if( 0 == status && -1 == go_back )
2065 go_back = i;
2066
2067 if( 0 == pMan->nPatterns || 0!=status || pMan->nPatterns % (64 * p->nSimWords-2) )
2068 continue;
2069
2070 if( -1 < go_back ){
2071 //printf("go back to %6d from %6d\n", go_back, i );
2072 pMan->nAndNodes -= i-go_back;
2073 i = go_back-1, go_back = -1;
2074 }
2075 }
2076 if ( p->iPatsPi > 0 )
2077 {
2078 abctime clk2 = Abc_Clock();
2079 Cec5_FlushCache2Pattern(pMan);
2080 Cec5_ManSimulate( p, pMan );
2081 p->iPatsPi = 0;
2082 pMan->simTravId = 0;
2083 pMan->simGlobalTop = 0;
2084 Cec5_ClearCexMarks(pMan);
2085 pMan->timeResimGlo += Abc_Clock() - clk2;
2086 if( -1 < go_back ){
2087 i = go_back - 1;
2088 go_back = -1;
2089 goto resume;
2090 }
2091 }
2092
2093 ABC_FREE(vMerged);
2094
2095 if ( pPars->fVerbose )
2096 Cec5_ManPrintStats( p, pPars, pMan, 0 );
2097 if ( ppNew )
2098 {
2099 Gia_ManForEachCo( p, pObj, i )
2100 pObj->Value = Gia_ManAppendCo( pMan->pNew, Gia_ObjFanin0Copy(pObj) );
2101 *ppNew = Gia_ManCleanup( pMan->pNew );
2102 }
2103
2104 if( fCbs ){
2105 if ( pPars->fVerbose ){
2106 CbsP_ManSatPrintStats( pCbs );
2107 CbsP_PrintRecord(&pCbs->Pars);
2108 }
2109 }
2110finalize:
2111 if ( pPars->fVerbose )
2112 printf( "SAT calls = %d: P = %d (0=%d a=%.2f m=%d) D = %d (0=%d a=%.2f m=%d) F = %d Sim = %d Recyc = %d Xor = %.2f %%\n",
2113 pMan->nSatUnsat + pMan->nSatSat + pMan->nSatUndec,
2114 pMan->nSatUnsat, pMan->nConflicts[1][0], (float)pMan->nConflicts[1][1]/Abc_MaxInt(1, pMan->nSatUnsat-pMan->nConflicts[1][0]), pMan->nConflicts[1][2],
2115 pMan->nSatSat, pMan->nConflicts[0][0], (float)pMan->nConflicts[0][1]/Abc_MaxInt(1, pMan->nSatSat -pMan->nConflicts[0][0]), pMan->nConflicts[0][2],
2116 pMan->nSatUndec,
2117 pMan->nSimulates, pMan->nRecycles, 100.0*pMan->nGates[1]/Abc_MaxInt(1, pMan->nGates[0]+pMan->nGates[1]) );
2118 Cec5_ManDestroy( pMan );
2119 if( pCbs )
2120 CbsP_ManStop(pCbs);
2121 //Gia_ManStaticFanoutStop( p );
2122 //Gia_ManEquivPrintClasses( p, 1, 0 );
2123 if ( p->pNexts ) Gia_ManRemoveWrongChoices( p );
2124 return p->pCexSeq ? 0 : 1;
2125}
2126Gia_Man_t * Cec5_ManSimulateTest( Gia_Man_t * p, Cec_ParFra_t * pPars, int fCbs, int approxLim, int subBatchSz, int adaRecycle )
2127{
2128 Gia_Man_t * pNew = NULL;
2129 Cec5_ManPerformSweeping( p, pPars, &pNew, 0, fCbs, approxLim, subBatchSz, adaRecycle );
2130 if ( pNew == NULL )
2131 pNew = Gia_ManDup( p );
2132 return pNew;
2133}
2134
2135
2136
2137int Cec5_ManSolveTwoCbs( Cec5_Man_t * p, CbsP_Man_t * pCbs, int iObj0, int iObj1, int fPhase, int * pfEasy, int fVerbose, int fEffort )
2138{
2139// abctime clk;
2140// int nBTLimit = fEffort ? p->pPars->nBTLimitPo : (Vec_BitEntry(p->vFails, iObj0) || Vec_BitEntry(p->vFails, iObj1)) ? Abc_MaxInt(1, p->pPars->nBTLimit/10) : p->pPars->nBTLimit;
2141 Gia_Obj_t * pRepr, * pObj;
2142 int nConfEnd, nConfBeg, status;//, iVar0, iVar1, Lits[2];
2143 int UnsatConflicts[3] = {0};
2144 //printf( "%d ", nBTLimit );
2145 if ( iObj1 < iObj0 )
2146 iObj1 ^= iObj0, iObj0 ^= iObj1, iObj1 ^= iObj0;
2147 assert( iObj0 < iObj1 );
2148 pRepr = Gia_ManObj( p->pNew, iObj0 );
2149 pObj = Gia_ManObj( p->pNew, iObj1 );
2150 *pfEasy = 0;
2151 // check if SAT solver needs recycling
2152 p->nCallsSince++;
2153// if ( p->nCallsSince > p->pPars->nCallsRecycle &&
2154// Vec_IntSize(&p->pNew->vSuppVars) > p->pPars->nSatVarMax && p->pPars->nSatVarMax )
2155// Cec5_ManSatSolverRecycle( p );
2156// // add more logic to the solver
2157// if ( !iObj0 && Cec5_ObjSatId(p->pNew, Gia_ManConst0(p->pNew)) == -1 )
2158// Cec5_ObjSetSatId( p->pNew, Gia_ManConst0(p->pNew), sat_solver_addvar(p->pSat) );
2159// clk = Abc_Clock();
2160// iVar0 = Cec5_ObjGetCnfVar( p, iObj0 );
2161// iVar1 = Cec5_ObjGetCnfVar( p, iObj1 );
2162// if( p->pPars->jType > 0 )
2163// {
2164// sat_solver_start_new_round( p->pSat );
2165// sat_solver_mark_cone( p->pSat, Cec5_ObjSatId(p->pNew, Gia_ManObj(p->pNew, iObj0)) );
2166// sat_solver_mark_cone( p->pSat, Cec5_ObjSatId(p->pNew, Gia_ManObj(p->pNew, iObj1)) );
2167// }
2168// p->timeCnf += Abc_Clock() - clk;
2169 // perform solving
2170// Lits[0] = Abc_Var2Lit(iVar0, 1);
2171// Lits[1] = Abc_Var2Lit(iVar1, fPhase);
2172// sat_solver_set_conflict_budget( p->pSat, nBTLimit );
2173// nConfBeg = sat_solver_conflictnum( p->pSat );
2174// status = sat_solver_solve( p->pSat, Lits, 2 );
2175// nConfEnd = sat_solver_conflictnum( p->pSat );
2176 nConfBeg = 0;
2177 if( !Gia_ObjIsConst0(pRepr) )
2178 status = CbsP_ManSolve2(pCbs,Gia_Not(pObj),Gia_NotCond(pRepr, fPhase));
2179 else
2180 status = CbsP_ManSolve2(pCbs,Gia_NotCond(pObj,fPhase),NULL);
2181 nConfEnd = pCbs->Pars.nBTThis;
2182 assert( nConfEnd >= nConfBeg );
2183 if ( fVerbose )
2184 {
2185 if ( status == CBS_SAT )
2186 {
2187 p->nConflicts[0][0] += nConfEnd == nConfBeg;
2188 p->nConflicts[0][1] += nConfEnd - nConfBeg;
2189 p->nConflicts[0][2] = Abc_MaxInt(p->nConflicts[0][2], nConfEnd - nConfBeg);
2190 *pfEasy = nConfEnd == nConfBeg;
2191 }
2192 else if ( status == CBS_UNSAT )
2193 {
2194 if ( iObj0 > 0 )
2195 {
2196 UnsatConflicts[0] = nConfEnd == nConfBeg;
2197 UnsatConflicts[1] = nConfEnd - nConfBeg;
2198 UnsatConflicts[2] = Abc_MaxInt(p->nConflicts[1][2], nConfEnd - nConfBeg);
2199 }
2200 else
2201 {
2202 p->nConflicts[1][0] += nConfEnd == nConfBeg;
2203 p->nConflicts[1][1] += nConfEnd - nConfBeg;
2204 p->nConflicts[1][2] = Abc_MaxInt(p->nConflicts[1][2], nConfEnd - nConfBeg);
2205 *pfEasy = nConfEnd == nConfBeg;
2206 }
2207 }
2208 }
2209 if ( status == CBS_UNSAT && iObj0 > 0 )
2210 {
2211 //Lits[0] = Abc_Var2Lit(iVar0, 0);
2212 //Lits[1] = Abc_Var2Lit(iVar1, !fPhase);
2213 //sat_solver_set_conflict_budget( p->pSat, nBTLimit );
2214 //nConfBeg = sat_solver_conflictnum( p->pSat );
2215 //status = sat_solver_solve( p->pSat, Lits, 2 );
2216 //nConfEnd = sat_solver_conflictnum( p->pSat );
2217 nConfBeg = 0;
2218 status = CbsP_ManSolve2(pCbs,pObj,Gia_NotCond(pRepr,!fPhase));
2219 nConfEnd = pCbs->Pars.nBTThis;
2220 assert( nConfEnd >= nConfBeg );
2221 if ( fVerbose )
2222 {
2223 if ( status == CBS_SAT )
2224 {
2225 p->nConflicts[0][0] += nConfEnd == nConfBeg;
2226 p->nConflicts[0][1] += nConfEnd - nConfBeg;
2227 p->nConflicts[0][2] = Abc_MaxInt(p->nConflicts[0][2], nConfEnd - nConfBeg);
2228 *pfEasy = nConfEnd == nConfBeg;
2229 }
2230 else if ( status == CBS_UNSAT )
2231 {
2232 UnsatConflicts[0] &= nConfEnd == nConfBeg;
2233 UnsatConflicts[1] += nConfEnd - nConfBeg;
2234 UnsatConflicts[2] = Abc_MaxInt(p->nConflicts[1][2], nConfEnd - nConfBeg);
2235
2236 p->nConflicts[1][0] += UnsatConflicts[0];
2237 p->nConflicts[1][1] += UnsatConflicts[1];
2238 p->nConflicts[1][2] = Abc_MaxInt(p->nConflicts[1][2], UnsatConflicts[2]);
2239 *pfEasy = UnsatConflicts[0];
2240 }
2241 }
2242 }
2243 //if ( status == GLUCOSE_UNDEC )
2244 // printf( "* " );
2245 return status;
2246}
2247
2248
2249int Cec5_ManSweepNodeCbs( Cec5_Man_t * p, CbsP_Man_t * pCbs, int iObj, int iRepr, int fTagFail )
2250{
2251 extern int CbsP_ManSolve2( CbsP_Man_t * p, Gia_Obj_t * pObj, Gia_Obj_t * pObj2 );
2252 abctime clk = Abc_Clock();
2253 int i, status, fEasy, RetValue = 1;
2254 Gia_Obj_t * pObj = Gia_ManObj( p->pAig, iObj );
2255 Gia_Obj_t * pRepr = Gia_ManObj( p->pAig, iRepr );
2256 int fCompl = Abc_LitIsCompl(pObj->Value) ^ Abc_LitIsCompl(pRepr->Value) ^ pObj->fPhase ^ pRepr->fPhase;
2257 //int fCompl = pObj->fPhase ^ pRepr->fPhase;
2258 int fEffort = p->vCoDrivers ? Vec_BitEntry(p->vCoDrivers, iObj) || Vec_BitEntry(p->vCoDrivers, iRepr) : 0;
2259 //status = Cec5_ManSolveTwo( p, Abc_Lit2Var(pRepr->Value), Abc_Lit2Var(pObj->Value), fCompl, &fEasy, p->pPars->fVerbose, fEffort );
2260
2261 status = Cec5_ManSolveTwoCbs( p, pCbs, Abc_Lit2Var(pRepr->Value), Abc_Lit2Var(pObj->Value), fCompl, &fEasy, p->pPars->fVerbose, fEffort );
2262 //status = CbsP_ManSolve2(pCbs,pObj,pRepr);
2263 if ( status == CBS_SAT )
2264 {
2265 int iLit;
2266 Vec_BitWriteEntry( p->vCexSite, iObj, 1 );
2267// int iPatsOld = p->pAig->iPatsPi;
2268// //printf( "Disproved: %d == %d.\n", Abc_Lit2Var(pRepr->Value), Abc_Lit2Var(pObj->Value) );
2269 p->nSatSat++;
2270 p->nPatterns++;
2271 Vec_IntClear( p->vPat );
2272 Vec_IntForEachEntry( pCbs->vModel, iLit, i )
2273 Vec_IntPush( p->vPat, Abc_LitNot(iLit) );
2274 assert( p->pAig->iPatsPi >= 0 && p->pAig->iPatsPi < 64 * p->pAig->nSimWords - 1 );
2275 p->pAig->iPatsPi++;
2276 Vec_IntForEachEntry( p->vPat, iLit, i )
2277 Vec_IntPush( p->vPiPatsCache, iLit );
2278 Vec_IntPush( p->vPiPatsCache, -1 );
2279
2280 if ( fEasy )
2281 p->timeSatSat0 += Abc_Clock() - clk;
2282 else
2283 p->timeSatSat += Abc_Clock() - clk;
2284 RetValue = 0;
2285
2286 p->simTravId = p->pAig->iPatsPi / p->LocalBatchSize;
2287 if( (p->pAig->iPatsPi % p->LocalBatchSize) == 0 || 1 == p->LocalBatchSize )
2288 Cec5_FlushCache2Pattern(p);
2289
2290// // this is not needed, but we keep it here anyway, because it takes very little time
2291// //Cec5_ManVerify( p->pNew, Abc_Lit2Var(pRepr->Value), Abc_Lit2Var(pObj->Value), fCompl, p->pSat );
2292// // resimulated once in a while
2293 Cec5_ManCheckGlobalSim(p);
2294 }
2295 else if ( status == CBS_UNSAT )
2296 {
2297 //printf( "Proved: %d == %d.\n", Abc_Lit2Var(pRepr->Value), Abc_Lit2Var(pObj->Value) );
2298 p->nSatUnsat++;
2299 pObj->Value = Abc_LitNotCond( pRepr->Value, fCompl );
2300 assert( !Gia_ObjProved( p->pAig, iObj ) );
2301 Gia_ObjSetProved( p->pAig, iObj );
2302 if ( iRepr == 0 )
2303 p->iLastConst = iObj;
2304 if ( fEasy )
2305 p->timeSatUnsat0 += Abc_Clock() - clk;
2306 else
2307 p->timeSatUnsat += Abc_Clock() - clk;
2308 RetValue = 1;
2309 }
2310 else
2311 {
2312 if( fTagFail ){
2313 p->nSatUndec++;
2314 assert( status == CBS_UNDEC );
2315 Gia_ObjSetFailed( p->pAig, iObj );
2316 Gia_ObjSetFailed( p->pAig, iRepr );
2317 Vec_BitWriteEntry( p->vFails, iObj, 1 );
2318 p->timeSatUndec += Abc_Clock() - clk;
2319 }
2320 //if ( iRepr )
2321 //Vec_BitWriteEntry( p->vFails, iRepr, 1 );
2322 RetValue = 2;
2323 }
2324 return RetValue;
2325}
2326Gia_Man_t * Cec5_ManSimulateTest3( Gia_Man_t * p, int nBTLimit, int fVerbose )
2327{
2328 int fCbs = 1, approxLim = 600, subBatchSz = 1, adaRecycle = 500;
2329 Gia_Man_t * pNew = NULL;
2330 Cec_ParFra_t ParsFra, * pPars = &ParsFra;
2331 Cec5_ManSetParams( pPars );
2332 pPars->fVerbose = fVerbose;
2333 pPars->nBTLimit = nBTLimit;
2334 Cec5_ManPerformSweeping( p, pPars, &pNew, 0, fCbs, approxLim, subBatchSz, adaRecycle );
2335 return pNew;
2336}
2337
2341
2342
2343ABC_NAMESPACE_IMPL_END
2344
bmcg2_sat_solver_markapprox
void bmcg2_sat_solver_markapprox(bmcg2_sat_solver *s, int v0, int v1, int nlim)
Definition AbcGlucose2.cpp:235
GLUCOSE_UNDEC
#define GLUCOSE_UNDEC
Definition AbcGlucose.h:36
GLUCOSE_UNSAT
#define GLUCOSE_UNSAT
INCLUDES ///.
Definition AbcGlucose.h:34
GLUCOSE_SAT
#define GLUCOSE_SAT
Definition AbcGlucose.h:35
nWords
int nWords
Definition abcNpn.c:127
Abc_RandomW
word Abc_RandomW(int fReset)
Definition utilSort.c:1022
ABC_SWAP
#define ABC_SWAP(Type, a, b)
Definition abc_global.h:253
abctime
ABC_INT64_T abctime
Definition abc_global.h:332
ABC_FALLOC
#define ABC_FALLOC(type, num)
Definition abc_global.h:266
ABC_ALLOC
#define ABC_ALLOC(type, num)
Definition abc_global.h:264
ABC_PRTP
#define ABC_PRTP(a, t, T)
Definition abc_global.h:258
Abc_Random
unsigned Abc_Random(int fReset)
Definition utilSort.c:1004
ABC_CALLOC
#define ABC_CALLOC(type, num)
Definition abc_global.h:265
ABC_FREE
#define ABC_FREE(obj)
Definition abc_global.h:267
ABC_NAMESPACE_IMPL_START
#define ABC_NAMESPACE_IMPL_START
Definition abc_namespaces.h:54
ABC_NAMESPACE_IMPL_END
#define ABC_NAMESPACE_IMPL_END
Definition abc_namespaces.h:55
timeSat
abctime timeSat
Definition abcDar.c:3942
Vec_Int_t
typedefABC_NAMESPACE_IMPL_START struct Vec_Int_t_ Vec_Int_t
DECLARATIONS ///.
Definition bblif.c:37
sat_solver_addvar
#define sat_solver_addvar
Definition cecSatG2.c:40
Gia_ManRemoveWrongChoices
void Gia_ManRemoveWrongChoices(Gia_Man_t *p)
Definition cecSatG2.c:1783
sat_solver
#define sat_solver
Definition cecSatG2.c:34
Cec5_ManCandIterStart
void Cec5_ManCandIterStart(Cec5_Man_t *p)
Definition cecSatG3.c:1450
Cec5_RefineOneClassIter
void Cec5_RefineOneClassIter(Gia_Man_t *p, int iRepr)
Definition cecSatG3.c:711
sat_solver_addclause
#define sat_solver_addclause
Definition cecSatG3.c:36
Cec5_ManCexVerify_rec
int Cec5_ManCexVerify_rec(Gia_Man_t *p, int iObj)
Definition cecSatG3.c:1174
Cec5_ManExtend
void Cec5_ManExtend(Cec5_Man_t *pMan, CbsP_Man_t *pCbs)
Definition cecSatG3.c:1862
Cec5_ManPackAddPattern
int Cec5_ManPackAddPattern(Gia_Man_t *p, Vec_Int_t *vLits, int fExtend)
Definition cecSatG3.c:1252
sat_solver_start
#define sat_solver_start
Definition cecSatG3.c:34
Cec5_ManCheckGlobalSim
void Cec5_ManCheckGlobalSim(Cec5_Man_t *p)
Definition cecSatG3.c:1690
Cec5_ClearCexMarks
void Cec5_ClearCexMarks(Cec5_Man_t *p)
Definition cecSatG3.c:1686
sat_solver_read_cex
#define sat_solver_read_cex
Definition cecSatG3.c:46
Cec5_ObjGetCnfVar
int Cec5_ObjGetCnfVar(Cec5_Man_t *p, int iObj)
Definition cecSatG3.c:565
sat_solver_addvar
#define sat_solver_addvar
Definition cecSatG3.c:39
sat_solver_set_conflict_budget
#define sat_solver_set_conflict_budget
Definition cecSatG3.c:42
Cec5_ManSimAlloc
void Cec5_ManSimAlloc(Gia_Man_t *p, int nWords, int fPrep)
Definition cecSatG3.c:1020
Cec5_ManGeneratePatternOne
int Cec5_ManGeneratePatternOne(Gia_Man_t *p, int iRepr, int iReprVal, int iCand, int iCandVal, Vec_Int_t *vPat, Vec_Int_t *vVisit)
Definition cecSatG3.c:1434
Cec5_ManSweepNode
int Cec5_ManSweepNode(Cec5_Man_t *p, int iObj, int iRepr)
Definition cecSatG3.c:1723
Cec5_ManGeneratePatterns_rec
int Cec5_ManGeneratePatterns_rec(Gia_Man_t *p, Gia_Obj_t *pObj, int Value, Vec_Int_t *vPat, Vec_Int_t *vVisit)
Definition cecSatG3.c:1320
Cec5_RefineInit
void Cec5_RefineInit(Gia_Man_t *p, Cec5_Man_t *pMan)
Definition cecSatG3.c:805
Cec5_ManDestroy
void Cec5_ManDestroy(Cec5_Man_t *p)
Definition cecSatG3.c:291
Cec5_ManSimHashKey
int Cec5_ManSimHashKey(word *pSim, int nSims, int nTableSize)
Definition cecSatG3.c:695
Cec5_ManSetParams
void Cec5_ManSetParams(Cec_ParFra_t *pPars)
Definition cecSatG3.c:222
Cec5_ManCexVerify
void Cec5_ManCexVerify(Gia_Man_t *p, int iObj0, int iObj1, int fPhase)
Definition cecSatG3.c:1189
sat_solver_reset
#define sat_solver_reset
Definition cecSatG3.c:41
Cec5_ManStartNew
Gia_Man_t * Cec5_ManStartNew(Gia_Man_t *pAig)
Definition cecSatG3.c:342
Cec5_ManPrintTfiConeStats
void Cec5_ManPrintTfiConeStats(Gia_Man_t *p)
Definition cecSatG3.c:1043
Cec5_ManPerformSweeping
int Cec5_ManPerformSweeping(Gia_Man_t *p, Cec_ParFra_t *pPars, Gia_Man_t **ppNew, int fSimOnly, int fCbs, int approxLim, int subBatchSz, int adaRecycle)
Definition cecSatG3.c:1872
Cec5_ManPackAddPatterns
void Cec5_ManPackAddPatterns(Gia_Man_t *p, int iBit, Vec_Int_t *vLits)
Definition cecSatG3.c:1212
Cec5_ManPrintClasses
void Cec5_ManPrintClasses(Gia_Man_t *p)
Definition cecSatG3.c:1115
Cec5_ManPrintStats
void Cec5_ManPrintStats(Gia_Man_t *p, Cec_ParFra_t *pPars, Cec5_Man_t *pMan, int fSim)
Definition cecSatG3.c:1067
Cec5_ManLoadInstance
void Cec5_ManLoadInstance(Cec5_Man_t *p, int iObj0, int iObj1, int *piVar0, int *piVar1)
Definition cecSatG3.c:1562
Cec5_ManSimulate
void Cec5_ManSimulate(Gia_Man_t *p, Cec5_Man_t *pMan)
Definition cecSatG3.c:971
Cec5_ManPackAddPatternTry
int Cec5_ManPackAddPatternTry(Gia_Man_t *p, int iBit, Vec_Int_t *vLits)
Definition cecSatG3.c:1230
Cec5_ManSolveTwo
int Cec5_ManSolveTwo(Cec5_Man_t *p, int iObj0, int iObj1, int fPhase, int *pfEasy, int fVerbose, int fEffort)
Definition cecSatG3.c:1575
Cec5_CollectSuper
void Cec5_CollectSuper(Gia_Obj_t *pObj, int fUseMuxes, Vec_Ptr_t *vSuper)
Definition cecSatG3.c:547
Cec5_AddClausesSuper
void Cec5_AddClausesSuper(Gia_Man_t *p, Gia_Obj_t *pNode, Vec_Ptr_t *vSuper, sat_solver *pSat)
Definition cecSatG3.c:479
Cec5_EvalPatterns
void Cec5_EvalPatterns(Gia_Man_t *p, Vec_Int_t *vPats, int nPats)
Definition cecSatG3.c:191
Cec5_ManGeneratePatterns
int Cec5_ManGeneratePatterns(Cec5_Man_t *p)
Definition cecSatG3.c:1484
sat_solver_set_var_fanin_lit
#define sat_solver_set_var_fanin_lit
Definition cecSatG3.c:49
sat_solver_read_cex_varvalue
#define sat_solver_read_cex_varvalue
Definition cecSatG3.c:40
Cec5_ManVerify
void Cec5_ManVerify(Gia_Man_t *p, int iObj0, int iObj1, int fPhase, sat_solver *pSat)
Definition cecSatG3.c:1150
Cec5_CollectSuper_rec
void Cec5_CollectSuper_rec(Gia_Obj_t *pObj, Vec_Ptr_t *vSuper, int fFirst, int fUseMuxes)
Definition cecSatG3.c:533
Cec5_ManFindRepr
Gia_Obj_t * Cec5_ManFindRepr(Gia_Man_t *p, Cec5_Man_t *pMan, int iObj)
Definition cecSatG3.c:1812
sat_solver_add_and
#define sat_solver_add_and
Definition cecSatG3.c:37
Cec5_RefineOneClass
void Cec5_RefineOneClass(Gia_Man_t *p, Cec5_Man_t *pMan, Vec_Int_t *vNodes)
Definition cecSatG3.c:749
Cec5_ObjAddToFrontier
void Cec5_ObjAddToFrontier(Gia_Man_t *p, Gia_Obj_t *pObj, Vec_Ptr_t *vFrontier, sat_solver *pSat)
Definition cecSatG3.c:554
sat_solver_conflictnum
#define sat_solver_conflictnum
Definition cecSatG3.c:43
Cec5_FlushCache2Pattern
void Cec5_FlushCache2Pattern(Cec5_Man_t *p)
Definition cecSatG3.c:1669
Cec5_ManCreate
Cec5_Man_t * Cec5_ManCreate(Gia_Man_t *pAig, Cec_ParFra_t *pPars)
Definition cecSatG3.c:248
Cec5_ManSimulateCis
void Cec5_ManSimulateCis(Gia_Man_t *p)
Definition cecSatG3.c:930
Cec5_Man_t
typedefABC_NAMESPACE_IMPL_START struct Cec5_Man_t_ Cec5_Man_t
DECLARATIONS ///.
Definition cecSatG3.c:87
sat_solver_add_xor
#define sat_solver_add_xor
Definition cecSatG3.c:38
Cec5_AddClausesMux
void Cec5_AddClausesMux(Gia_Man_t *p, Gia_Obj_t *pNode, sat_solver *pSat)
Definition cecSatG3.c:371
Cec5_RefineClasses
void Cec5_RefineClasses(Gia_Man_t *p, Cec5_Man_t *pMan, Vec_Int_t *vClasses)
Definition cecSatG3.c:777
Cec5_ManVerify_rec
int Cec5_ManVerify_rec(Gia_Man_t *p, int iObj, sat_solver *pSat)
Definition cecSatG3.c:1135
sat_solver_stop
#define sat_solver_stop
Definition cecSatG3.c:35
sat_solver
#define sat_solver
Definition cecSatG3.c:33
Cec5_ManSimulateTest
Gia_Man_t * Cec5_ManSimulateTest(Gia_Man_t *p, Cec_ParFra_t *pPars, int fCbs, int approxLim, int subBatchSz, int adaRecycle)
Definition cecSatG3.c:2126
Cec5_ManPrintClasses2
void Cec5_ManPrintClasses2(Gia_Man_t *p)
Definition cecSatG3.c:1104
Cec5_ManCandIterNext
int Cec5_ManCandIterNext(Cec5_Man_t *p)
Definition cecSatG3.c:1466
Cec5_ManSimulateTest3
Gia_Man_t * Cec5_ManSimulateTest3(Gia_Man_t *p, int nBTLimit, int fVerbose)
Definition cecSatG3.c:2326
Cec5_EvalCombine
Vec_Wrd_t * Cec5_EvalCombine(Vec_Int_t *vPats, int nPats, int nInputs, int nWords)
FUNCTION DEFINITIONS ///.
Definition cecSatG3.c:174
sat_solver_solve
#define sat_solver_solve
Definition cecSatG3.c:44
Cec5_ManSimulate_rec
void Cec5_ManSimulate_rec(Gia_Man_t *p, Cec5_Man_t *pMan, int iObj)
Definition cecSatG3.c:1000
Cec5_ManClearCis
void Cec5_ManClearCis(Gia_Man_t *p)
Definition cecSatG3.c:937
Cec5_ManSweepNodeCbs
int Cec5_ManSweepNodeCbs(Cec5_Man_t *p, CbsP_Man_t *pCbs, int iObj, int iRepr, int fTagFail)
Definition cecSatG3.c:2249
sat_solver_set_jftr
#define sat_solver_set_jftr
Definition cecSatG3.c:48
Cec5_ManSimulateCos
int Cec5_ManSimulateCos(Gia_Man_t *p)
Definition cecSatG3.c:957
Cec5_ManSolveTwoCbs
int Cec5_ManSolveTwoCbs(Cec5_Man_t *p, CbsP_Man_t *pCbs, int iObj0, int iObj1, int fPhase, int *pfEasy, int fVerbose, int fEffort)
Definition cecSatG3.c:2137
Cec5_ManSatSolverRecycle
void Cec5_ManSatSolverRecycle(Cec5_Man_t *p)
Definition cecSatG3.c:1545
Cec5_ManDeriveCex
Abc_Cex_t * Cec5_ManDeriveCex(Gia_Man_t *p, int iOut, int iPat)
Definition cecSatG3.c:944
Cec_ParFra_t
struct Cec_ParFra_t_ Cec_ParFra_t
Definition cec.h:96
p
Cube * p
Definition exorList.c:222
CbsP_ManAlloc
CbsP_Man_t * CbsP_ManAlloc(Gia_Man_t *pGia)
Definition giaCSatP.c:173
CbsP_PrintRecord
void CbsP_PrintRecord(CbsP_Par_t *pPars)
Definition giaCSatP.c:148
CbsP_ManStop
void CbsP_ManStop(CbsP_Man_t *p)
Definition giaCSatP.c:204
CbsP_ManSatPrintStats
void CbsP_ManSatPrintStats(CbsP_Man_t *p)
Definition giaCSatP.c:1073
CbsP_ManSolve2
int CbsP_ManSolve2(CbsP_Man_t *p, Gia_Obj_t *pObj, Gia_Obj_t *pObj2)
Definition giaCSatP.c:1017
CBS_UNSAT
#define CBS_UNSAT
Definition giaCSatP.h:110
CbsP_Man_t
struct CbsP_Man_t_ CbsP_Man_t
Definition giaCSatP.h:75
CBS_UNDEC
#define CBS_UNDEC
Definition giaCSatP.h:112
CBS_SAT
#define CBS_SAT
Definition giaCSatP.h:111
Gia_Rpr_t
struct Gia_Rpr_t_ Gia_Rpr_t
Definition gia.h:57
Gia_ManDup
Gia_Man_t * Gia_ManDup(Gia_Man_t *p)
Definition giaDup.c:720
Gia_ManSimPatSimOut
Vec_Wrd_t * Gia_ManSimPatSimOut(Gia_Man_t *pGia, Vec_Wrd_t *vSimsPi, int fOuts)
Definition giaSimBase.c:138
Gia_ObjRecognizeMux
Gia_Obj_t * Gia_ObjRecognizeMux(Gia_Obj_t *pNode, Gia_Obj_t **ppNodeT, Gia_Obj_t **ppNodeE)
Definition giaUtil.c:1056
Gia_ManForEachAnd
#define Gia_ManForEachAnd(p, pObj, i)
Definition gia.h:1214
Gia_ManForEachCoId
#define Gia_ManForEachCoId(p, Id, i)
Definition gia.h:1240
Gia_ManStopP
void Gia_ManStopP(Gia_Man_t **p)
Definition giaMan.c:224
Gia_ManSetRegNum
void Gia_ManSetRegNum(Gia_Man_t *p, int nRegs)
Definition giaMan.c:764
Gia_ManForEachCoDriverId
#define Gia_ManForEachCoDriverId(p, DriverId, i)
Definition gia.h:1246
Gia_ManHashAlloc
void Gia_ManHashAlloc(Gia_Man_t *p)
Definition giaHash.c:105
Gia_ClassForEachObj1
#define Gia_ClassForEachObj1(p, i, iObj)
Definition gia.h:1109
Gia_ManStart
Gia_Man_t * Gia_ManStart(int nObjsMax)
FUNCTION DEFINITIONS ///.
Definition giaMan.c:57
Gia_Obj_t
struct Gia_Obj_t_ Gia_Obj_t
Definition gia.h:76
Gia_ManFillValue
void Gia_ManFillValue(Gia_Man_t *p)
Definition giaUtil.c:369
Gia_Man_t
struct Gia_Man_t_ Gia_Man_t
Definition gia.h:96
Gia_ManForEachObjVec
#define Gia_ManForEachObjVec(vVec, p, pObj, i)
Definition gia.h:1194
Gia_ManCleanup
Gia_Man_t * Gia_ManCleanup(Gia_Man_t *p)
Definition giaScl.c:84
Gia_ManCleanMark0
void Gia_ManCleanMark0(Gia_Man_t *p)
Definition giaUtil.c:256
Gia_ManCollectTfi
void Gia_ManCollectTfi(Gia_Man_t *p, Vec_Int_t *vRoots, Vec_Int_t *vNodes)
Definition giaDfs.c:581
Gia_ObjRecognizeExor
int Gia_ObjRecognizeExor(Gia_Obj_t *pObj, Gia_Obj_t **ppFan0, Gia_Obj_t **ppFan1)
Definition giaUtil.c:1018
Gia_ManHashAnd
int Gia_ManHashAnd(Gia_Man_t *p, int iLit0, int iLit1)
Definition giaHash.c:576
Gia_ManIncrementTravId
void Gia_ManIncrementTravId(Gia_Man_t *p)
Definition giaUtil.c:190
Gia_ManHashXorReal
int Gia_ManHashXorReal(Gia_Man_t *p, int iLit0, int iLit1)
Definition giaHash.c:469
Gia_ManForEachObj
#define Gia_ManForEachObj(p, pObj, i)
MACRO DEFINITIONS ///.
Definition gia.h:1190
Gia_ManForEachCo
#define Gia_ManForEachCo(p, pObj, i)
Definition gia.h:1236
Gia_ManForEachCi
#define Gia_ManForEachCi(p, pObj, i)
Definition gia.h:1228
Gia_ManSetPhase
void Gia_ManSetPhase(Gia_Man_t *p)
Definition giaUtil.c:420
GIA_VOID
#define GIA_VOID
Definition gia.h:46
Gia_ManCleanMark01
void Gia_ManCleanMark01(Gia_Man_t *p)
Definition giaUtil.c:218
Gia_ManLevelNum
int Gia_ManLevelNum(Gia_Man_t *p)
Definition giaUtil.c:546
Gia_ManForEachClass0
#define Gia_ManForEachClass0(p, i)
Definition gia.h:1103
Gia_ManForEachCiId
#define Gia_ManForEachCiId(p, Id, i)
Definition gia.h:1230
Gia_ManCleanMark1
void Gia_ManCleanMark1(Gia_Man_t *p)
Definition giaUtil.c:313
word
unsigned __int64 word
DECLARATIONS ///.
Definition kitPerm.c:36
timeOther
abctime timeOther
Definition llb3Image.c:82
CbsP_Man_t_::vModel
Vec_Int_t * vModel
Definition giaCSatP.h:86
CbsP_Man_t_::Pars
CbsP_Par_t Pars
Definition giaCSatP.h:78
CbsP_Man_t_::vValue
Vec_Int_t * vValue
Definition giaCSatP.h:85
CbsP_Man_t_::pAig
Gia_Man_t * pAig
Definition giaCSatP.h:79
Cec5_Man_t_
Definition cecSatG3.c:89
Cec5_Man_t_::iLastConst
int iLastConst
Definition cecSatG3.c:108
Cec5_Man_t_::timeSim
abctime timeSim
Definition cecSatG3.c:136
Cec5_Man_t_::vPiPatsCache
Vec_Int_t * vPiPatsCache
Definition cecSatG3.c:143
Cec5_Man_t_::nGates
int nGates[2]
Definition cecSatG3.c:127
Cec5_Man_t_::vClassUpdates
Vec_Int_t * vClassUpdates
Definition cecSatG3.c:98
Cec5_Man_t_::nSimulates
int nSimulates
Definition cecSatG3.c:124
Cec5_Man_t_::nSatSat
int nSatSat
Definition cecSatG3.c:120
Cec5_Man_t_::nAndNodes
int nAndNodes
Definition cecSatG3.c:118
Cec5_Man_t_::timeRefine
abctime timeRefine
Definition cecSatG3.c:137
Cec5_Man_t_::pTable
int * pTable
Definition cecSatG3.c:113
Cec5_Man_t_::nRecycles
int nRecycles
Definition cecSatG3.c:125
Cec5_Man_t_::vRefBins
Vec_Int_t * vRefBins
Definition cecSatG3.c:112
Cec5_Man_t_::pPars
Cec_ParFra_t * pPars
Definition cecSatG3.c:90
Cec5_Man_t_::simStart
int simStart
Definition cecSatG3.c:148
Cec5_Man_t_::simTravId
int simTravId
Definition cecSatG3.c:142
Cec5_Man_t_::vPat
Vec_Int_t * vPat
Definition cecSatG3.c:102
Cec5_Man_t_::fEec
int fEec
Definition cecSatG3.c:144
Cec5_Man_t_::timeStart
abctime timeStart
Definition cecSatG3.c:140
Cec5_Man_t_::vDisprPairs
Vec_Int_t * vDisprPairs
Definition cecSatG3.c:103
Cec5_Man_t_::vCexSite
Vec_Bit_t * vCexSite
Definition cecSatG3.c:146
Cec5_Man_t_::nConflicts
int nConflicts[3][3]
Definition cecSatG3.c:126
Cec5_Man_t_::nTableSize
int nTableSize
Definition cecSatG3.c:114
Cec5_Man_t_::simBatchFactor
int simBatchFactor
Definition cecSatG3.c:151
Cec5_Man_t_::pSat
sat_solver * pSat
Definition cecSatG3.c:94
Cec5_Man_t_::nSatUnsat
int nSatUnsat
Definition cecSatG3.c:121
Cec5_Man_t_::simGlobalTop
int simGlobalTop
Definition cecSatG3.c:150
Cec5_Man_t_::iPosRead
int iPosRead
Definition cecSatG3.c:106
Cec5_Man_t_::timeResimGlo
abctime timeResimGlo
Definition cecSatG3.c:138
Cec5_Man_t_::pNew
Gia_Man_t * pNew
Definition cecSatG3.c:92
Cec5_Man_t_::timeSatSat
abctime timeSatSat
Definition cecSatG3.c:133
Cec5_Man_t_::vCands
Vec_Int_t * vCands
Definition cecSatG3.c:100
Cec5_Man_t_::vFails
Vec_Bit_t * vFails
Definition cecSatG3.c:104
Cec5_Man_t_::nItersSat
int nItersSat
Definition cecSatG3.c:117
Cec5_Man_t_::timeResimLoc
abctime timeResimLoc
Definition cecSatG3.c:139
Cec5_Man_t_::nSatUndec
int nSatUndec
Definition cecSatG3.c:122
Cec5_Man_t_::timeSatSat0
abctime timeSatSat0
Definition cecSatG3.c:131
Cec5_Man_t_::vCoDrivers
Vec_Bit_t * vCoDrivers
Definition cecSatG3.c:105
Cec5_Man_t_::pAig
Gia_Man_t * pAig
Definition cecSatG3.c:91
Cec5_Man_t_::timeSatUnsat0
abctime timeSatUnsat0
Definition cecSatG3.c:132
Cec5_Man_t_::simBound
int simBound
Definition cecSatG3.c:147
Cec5_Man_t_::nFaster
int nFaster[2]
Definition cecSatG3.c:128
Cec5_Man_t_::timeSatUndec
abctime timeSatUndec
Definition cecSatG3.c:135
Cec5_Man_t_::nItersSim
int nItersSim
Definition cecSatG3.c:116
Cec5_Man_t_::timeSatUnsat
abctime timeSatUnsat
Definition cecSatG3.c:134
Cec5_Man_t_::nPatterns
int nPatterns
Definition cecSatG3.c:119
Cec5_Man_t_::nCallsSince
int nCallsSince
Definition cecSatG3.c:123
Cec5_Man_t_::vRefClasses
Vec_Int_t * vRefClasses
Definition cecSatG3.c:110
Cec5_Man_t_::vFrontier
Vec_Ptr_t * vFrontier
Definition cecSatG3.c:95
Cec5_Man_t_::vFanins
Vec_Ptr_t * vFanins
Definition cecSatG3.c:96
Cec5_Man_t_::iPosWrite
int iPosWrite
Definition cecSatG3.c:107
Cec5_Man_t_::LocalBatchSize
int LocalBatchSize
Definition cecSatG3.c:145
Cec5_Man_t_::vRefNodes
Vec_Int_t * vRefNodes
Definition cecSatG3.c:111
Cec5_Man_t_::timeCnf
abctime timeCnf
Definition cecSatG3.c:129
Cec5_Man_t_::vCexMin
Vec_Int_t * vCexMin
Definition cecSatG3.c:97
Cec5_Man_t_::vCexStamps
Vec_Int_t * vCexStamps
Definition cecSatG3.c:99
Cec5_Man_t_::adaRecycle
int adaRecycle
Definition cecSatG3.c:152
Cec5_Man_t_::timeGenPats
abctime timeGenPats
Definition cecSatG3.c:130
Cec5_Man_t_::approxLim
int approxLim
Definition cecSatG3.c:149
Cec5_Man_t_::vVisit
Vec_Int_t * vVisit
Definition cecSatG3.c:101
Cec_ParFra_t_::fCheckMiter
int fCheckMiter
Definition cec.h:112
Cec_ParFra_t_::nBTLimit
int nBTLimit
Definition cec.h:103
Cec_ParFra_t_::nWords
int nWords
Definition cec.h:100
Cec_ParFra_t_::nBTLimitPo
int nBTLimitPo
Definition cec.h:104
Cec_ParFra_t_::nLevelMax
int nLevelMax
Definition cec.h:106
Cec_ParFra_t_::nItersMax
int nItersMax
Definition cec.h:102
Cec_ParFra_t_::nRounds
int nRounds
Definition cec.h:101
Cec_ParFra_t_::nSatVarMax
int nSatVarMax
Definition cec.h:109
Cec_ParFra_t_::nGenIters
int nGenIters
Definition cec.h:110
Cec_ParFra_t_::jType
int jType
Definition cec.h:99
Cec_ParFra_t_::nCallsRecycle
int nCallsRecycle
Definition cec.h:108
Cec_ParFra_t_::fVerbose
int fVerbose
Definition cec.h:121
Cec_ParFra_t_::fSatSweeping
int fSatSweeping
Definition cec.h:116
Gia_Man_t_::vCopies2
Vec_Int_t vCopies2
Definition gia.h:153
Gia_Man_t_::pMuxes
unsigned * pMuxes
Definition gia.h:106
Gia_Man_t_::pSpec
char * pSpec
Definition gia.h:100
Gia_Man_t_::nObjsAlloc
int nObjsAlloc
Definition gia.h:104
Gia_Man_t_::pName
char * pName
Definition gia.h:99
Gia_Obj_t_::fMark1
unsigned fMark1
Definition gia.h:86
Gia_Obj_t_::Value
unsigned Value
Definition gia.h:89
Gia_Obj_t_::fPhase
unsigned fPhase
Definition gia.h:87
Gia_Obj_t_::fMark0
unsigned fMark0
Definition gia.h:81
Abc_CexAlloc
ABC_NAMESPACE_IMPL_START Abc_Cex_t * Abc_CexAlloc(int nRegs, int nRealPis, int nFrames)
DECLARATIONS ///.
Definition utilCex.c:51
Abc_Cex_t
typedefABC_NAMESPACE_HEADER_START struct Abc_Cex_t_ Abc_Cex_t
INCLUDES ///.
Definition utilCex.h:39
assert
#define assert(ex)
Definition util_old.h:213
memset
char * memset()
Vec_Bit_t
typedefABC_NAMESPACE_HEADER_START struct Vec_Bit_t_ Vec_Bit_t
INCLUDES ///.
Definition vecBit.h:42
Vec_IntForEachEntryDouble
#define Vec_IntForEachEntryDouble(vVec, Entry1, Entry2, i)
Definition vecInt.h:72
Vec_IntForEachEntry
#define Vec_IntForEachEntry(vVec, Entry, i)
MACRO DEFINITIONS ///.
Definition vecInt.h:54
Vec_IntForEachEntryReverse
#define Vec_IntForEachEntryReverse(vVec, pEntry, i)
Definition vecInt.h:62
Vec_Ptr_t
typedefABC_NAMESPACE_HEADER_START struct Vec_Ptr_t_ Vec_Ptr_t
INCLUDES ///.
Definition vecPtr.h:42
Vec_PtrForEachEntry
#define Vec_PtrForEachEntry(Type, vVec, pEntry, i)
MACRO DEFINITIONS ///.
Definition vecPtr.h:55
Vec_Wrd_t
typedefABC_NAMESPACE_HEADER_START struct Vec_Wrd_t_ Vec_Wrd_t
INCLUDES ///.
Definition vecWrd.h:42