ABC: A System for Sequential Synthesis and Verification
 
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fpgaCore.c
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1
18
19#include "fpgaInt.h"
20
22
23
27
28static int Fpga_MappingPostProcess( Fpga_Man_t * p );
29
30extern clock_t s_MappingTime;
31extern int s_MappingMem;
32
33
37
54{
55 clock_t clk, clkTotal = clock();
56
57 // collect the nodes reachable from POs in the DFS order (including the choices)
58 p->vAnds = Fpga_MappingDfs( p, 1 );
59 Fpga_ManReportChoices( p ); // recomputes levels
61
62 // compute the cuts of nodes in the DFS order
63 clk = clock();
65 p->timeCuts = clock() - clk;
66
67 // match the truth tables to the supergates
68 clk = clock();
69 if ( !Fpga_MappingMatches( p, 1 ) )
70 return 0;
71 p->timeMatch = clock() - clk;
72
73 // perform area recovery
74 clk = clock();
75 if ( !Fpga_MappingPostProcess( p ) )
76 return 0;
77 p->timeRecover = clock() - clk;
78//ABC_PRT( "Total mapping time", clock() - clkTotal );
79
80 s_MappingTime = clock() - clkTotal;
81 s_MappingMem = Fpga_CutCountAll(p) * (sizeof(Fpga_Cut_t) - sizeof(int) * (FPGA_MAX_LEAVES - p->nVarsMax));
82
83 // print the AI-graph used for mapping
84 //Fpga_ManShow( p, "test" );
85// if ( p->fVerbose )
86// Fpga_MappingPrintOutputArrivals( p );
87 if ( p->fVerbose )
88 {
89 ABC_PRT( "Total time", clock() - clkTotal );
90 }
91 return 1;
92}
93
109int Fpga_MappingPostProcess( Fpga_Man_t * p )
110{
111 int fShowSwitching = 0;
112 int fRecoverAreaFlow = 1;
113 int fRecoverArea = 1;
114 float aAreaTotalCur, aAreaTotalCur2;
115 int Iter;
116 clock_t clk;
117
118//if ( p->fVerbose )
119// printf( "Best clock period = %5.2f\n", Fpga_TimeComputeArrivalMax(p) );
120
121 // compute area, set references, and collect nodes used in the mapping
122 Iter = 1;
123 aAreaTotalCur = Fpga_MappingSetRefsAndArea( p );
124if ( p->fVerbose )
125{
126printf( "Iteration %dD : Area = %8.1f ", Iter++, aAreaTotalCur );
127if ( fShowSwitching )
128printf( "Switch = %8.1f ", Fpga_MappingGetSwitching(p,p->vMapping) );
129else
130printf( "Delay = %5.2f ", Fpga_TimeComputeArrivalMax(p) );
131
132ABC_PRT( "Time", p->timeMatch );
133}
134
135 if ( !p->fAreaRecovery )
136 return 1;
137
138 if ( fRecoverAreaFlow )
139 {
140clk = clock();
141 // compute the required times and the fanouts
143 // remap topologically
145 // get the resulting area
146// aAreaTotalCur = Fpga_MappingSetRefsAndArea( p );
147 aAreaTotalCur = Fpga_MappingAreaTrav( p );
148 // note that here we do not update the reference counter
149 // for some reason, this works better on benchmarks
150if ( p->fVerbose )
151{
152printf( "Iteration %dF : Area = %8.1f ", Iter++, aAreaTotalCur );
153if ( fShowSwitching )
154printf( "Switch = %8.1f ", Fpga_MappingGetSwitching(p,p->vMapping) );
155else
156printf( "Delay = %5.2f ", Fpga_TimeComputeArrivalMax(p) );
157ABC_PRT( "Time", clock() - clk );
158}
159 }
160
161 // update reference counters
162 aAreaTotalCur2 = Fpga_MappingSetRefsAndArea( p );
163 assert( aAreaTotalCur == aAreaTotalCur2 );
164
165 if ( fRecoverArea )
166 {
167clk = clock();
168 // compute the required times and the fanouts
170 // remap topologically
171 if ( p->fSwitching )
173 else
175 // get the resulting area
176 aAreaTotalCur = Fpga_MappingSetRefsAndArea( p );
177if ( p->fVerbose )
178{
179printf( "Iteration %d%s : Area = %8.1f ", Iter++, (p->fSwitching?"S":"A"), aAreaTotalCur );
180if ( fShowSwitching )
181printf( "Switch = %8.1f ", Fpga_MappingGetSwitching(p,p->vMapping) );
182else
183printf( "Delay = %5.2f ", Fpga_TimeComputeArrivalMax(p) );
184ABC_PRT( "Time", clock() - clk );
185}
186 }
187
188 p->fAreaGlo = aAreaTotalCur;
189 return 1;
190}
191
192
194
#define ABC_PRT(a, t)
Definition abc_global.h:255
#define ABC_NAMESPACE_IMPL_START
#define ABC_NAMESPACE_IMPL_END
Cube * p
Definition exorList.c:222
int Fpga_Mapping(Fpga_Man_t *p)
FUNCTION DEFINITIONS ///.
Definition fpgaCore.c:53
int Fpga_CutCountAll(Fpga_Man_t *pMan)
Definition fpgaCut.c:767
void Fpga_MappingCuts(Fpga_Man_t *p)
FUNCTION DEFINITIONS ///.
Definition fpgaCut.c:130
void Fpga_ManReportChoices(Fpga_Man_t *pMan)
Definition fpgaUtils.c:897
float Fpga_MappingAreaTrav(Fpga_Man_t *pMan)
Definition fpgaUtils.c:239
float Fpga_TimeComputeArrivalMax(Fpga_Man_t *p)
Definition fpgaTime.c:89
int Fpga_MappingMatchesSwitch(Fpga_Man_t *p)
Definition fpgaMatch.c:349
float Fpga_MappingSetRefsAndArea(Fpga_Man_t *pMan)
Definition fpgaUtils.c:299
void Fpga_TimeComputeRequiredGlobal(Fpga_Man_t *p, int fFirstTime)
Definition fpgaTime.c:136
int Fpga_MappingMatches(Fpga_Man_t *p, int fDelayOriented)
FUNCTION DEFINITIONS ///.
Definition fpgaMatch.c:67
void Fpga_MappingSetChoiceLevels(Fpga_Man_t *pMan)
Definition fpgaUtils.c:876
Fpga_NodeVec_t * Fpga_MappingDfs(Fpga_Man_t *pMan, int fCollectEquiv)
FUNCTION DEFINITIONS ///.
Definition fpgaUtils.c:54
#define FPGA_MAX_LEAVES
INCLUDES ///.
Definition fpgaInt.h:52
int Fpga_MappingMatchesArea(Fpga_Man_t *p)
Definition fpgaMatch.c:196
float Fpga_MappingGetSwitching(Fpga_Man_t *pMan, Fpga_NodeVec_t *vMapping)
Definition fpgaSwitch.c:127
struct Fpga_ManStruct_t_ Fpga_Man_t
STRUCTURE DEFINITIONS ///.
Definition fpga.h:43
struct Fpga_CutStruct_t_ Fpga_Cut_t
Definition fpga.h:46
abctime s_MappingTime
DECLARATIONS ///.
Definition abcPrint.c:47
int s_MappingMem
Definition abcPrint.c:48
#define assert(ex)
Definition util_old.h:213