ABC: A System for Sequential Synthesis and Verification
 
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cgtDecide.c
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1
20
21#include "cgtInt.h"
22#include "proof/ssw/sswInt.h"
23
25
26
30
31extern int Ssw_SmlCheckXorImplication( Ssw_Sml_t * p, Aig_Obj_t * pObjLi, Aig_Obj_t * pObjLo, Aig_Obj_t * pCand );
32extern int Ssw_SmlCountXorImplication( Ssw_Sml_t * p, Aig_Obj_t * pObjLi, Aig_Obj_t * pObjLo, Aig_Obj_t * pCand );
33extern int Ssw_SmlCountEqual( Ssw_Sml_t * p, Aig_Obj_t * pObjLi, Aig_Obj_t * pObjLo );
34extern int Ssw_SmlNodeCountOnesReal( Ssw_Sml_t * p, Aig_Obj_t * pObj );
35extern int Ssw_SmlNodeCountOnesRealVec( Ssw_Sml_t * p, Vec_Ptr_t * vObjs );
36
40
53{
54 Aig_Obj_t * pFanout;
55 int f, iFanout = -1;
56 if ( Aig_ObjIsTravIdCurrent(pAig, pObj) )
57 return;
58 Aig_ObjSetTravIdCurrent(pAig, pObj);
59 if ( Aig_ObjIsCo(pObj) )
60 {
61 Vec_PtrPush( vFanout, pObj );
62 return;
63 }
64 Aig_ObjForEachFanout( pAig, pObj, pFanout, iFanout, f )
65 Cgt_ManCollectFanoutPos_rec( pAig, pFanout, vFanout );
66}
67
79void Cgt_ManCollectFanoutPos( Aig_Man_t * pAig, Aig_Obj_t * pObj, Vec_Ptr_t * vFanout )
80{
81 Vec_PtrClear( vFanout );
83 Cgt_ManCollectFanoutPos_rec( pAig, pObj, vFanout );
84}
85
97int Cgt_ManCheckGateComplete( Aig_Man_t * pAig, Vec_Vec_t * vGatesAll, Aig_Obj_t * pGate, Vec_Ptr_t * vFanout )
98{
99 Vec_Ptr_t * vGates;
100 Aig_Obj_t * pObj;
101 int i;
102 Vec_PtrForEachEntry( Aig_Obj_t *, vFanout, pObj, i )
103 {
104 if ( Saig_ObjIsPo(pAig, pObj) )
105 return 0;
106 vGates = Vec_VecEntry( vGatesAll, Aig_ObjCioId(pObj) - Saig_ManPoNum(pAig) );
107 if ( Vec_PtrFind( vGates, pGate ) == -1 )
108 return 0;
109 }
110 return 1;
111}
112
124Vec_Ptr_t * Cgt_ManCompleteGates( Aig_Man_t * pAig, Vec_Vec_t * vGatesAll, int nOdcMax, int fVerbose )
125{
126 Vec_Ptr_t * vFanout, * vGatesFull;
127 Aig_Obj_t * pGate, * pGateR;
128 int i, k;
129 vFanout = Vec_PtrAlloc( 100 );
130 vGatesFull = Vec_PtrAlloc( 100 );
131 Vec_VecForEachEntry( Aig_Obj_t *, vGatesAll, pGate, i, k )
132 {
133 pGateR = Aig_Regular(pGate);
134 if ( pGateR->fMarkA )
135 continue;
136 pGateR->fMarkA = 1;
137 Cgt_ManCollectFanoutPos( pAig, pGateR, vFanout );
138 if ( Cgt_ManCheckGateComplete( pAig, vGatesAll, pGate, vFanout ) )
139 Vec_PtrPush( vGatesFull, pGate );
140 }
141 Vec_PtrFree( vFanout );
142 Vec_VecForEachEntry( Aig_Obj_t *, vGatesAll, pGate, i, k )
143 Aig_Regular(pGate)->fMarkA = 0;
144 return vGatesFull;
145}
146
159{
160 int nFrames = 32;
161 int nWords = 1;
162 Ssw_Sml_t * pSml;
163 Vec_Ptr_t * vOne;
164 int i, nTransSaved = 0;
165 pSml = Ssw_SmlSimulateSeq( pAig, 0, nFrames, nWords );
166 Vec_VecForEachLevel( vGates, vOne, i )
167 nTransSaved += Ssw_SmlNodeCountOnesRealVec( pSml, vOne );
168 Ssw_SmlStop( pSml );
169 return (float)100.0*nTransSaved/32/nFrames/nWords/Vec_VecSize(vGates);
170}
171
184Vec_Vec_t * Cgt_ManDecideSimple( Aig_Man_t * pAig, Vec_Vec_t * vGatesAll, int nOdcMax, int fVerbose )
185{
186 int nFrames = 32;
187 int nWords = 1;
188 Ssw_Sml_t * pSml;
189 Vec_Vec_t * vGates;
190 Vec_Ptr_t * vCands;
191 Aig_Obj_t * pObjLi, * pObjLo, * pCand, * pCandBest;
192 int i, k, nHitsCur, nHitsMax, Counter = 0;
193 abctime clk = Abc_Clock();
194 int nTransTotal = 0, nTransSaved = 0;
195 vGates = Vec_VecStart( Saig_ManRegNum(pAig) );
196 pSml = Ssw_SmlSimulateSeq( pAig, 0, nFrames, nWords );
197 Saig_ManForEachLiLo( pAig, pObjLi, pObjLo, i )
198 {
199 nHitsMax = 0;
200 pCandBest = NULL;
201 vCands = Vec_VecEntry( vGatesAll, i );
202 Vec_PtrForEachEntry( Aig_Obj_t *, vCands, pCand, k )
203 {
204 // check if this is indeed a clock-gate
205 if ( nOdcMax == 0 && !Ssw_SmlCheckXorImplication( pSml, pObjLi, pObjLo, pCand ) )
206 printf( "Clock gate candidate is invalid!\n" );
207 // find its characteristic number
208 nHitsCur = Ssw_SmlNodeCountOnesReal( pSml, pCand );
209 if ( nHitsMax < nHitsCur )
210 {
211 nHitsMax = nHitsCur;
212 pCandBest = pCand;
213 }
214 }
215 if ( pCandBest != NULL )
216 {
217 Vec_VecPush( vGates, i, pCandBest );
218 Counter++;
219 nTransSaved += nHitsMax;
220 }
221 nTransTotal += 32 * nFrames * nWords;
222 }
223 Ssw_SmlStop( pSml );
224 if ( fVerbose )
225 {
226 printf( "Gating signals = %6d. Gated flops = %6d. (Total flops = %6d.)\n",
227 Vec_VecSizeSize(vGatesAll), Counter, Saig_ManRegNum(pAig) );
228// printf( "Gated transitions = %5.2f %%. (%5.2f %%.) ",
229// 100.0*nTransSaved/nTransTotal, Cgt_ManComputeCoverage(pAig, vGates) );
230 printf( "Gated transitions = %5.2f %%. ", Cgt_ManComputeCoverage(pAig, vGates) );
231 ABC_PRT( "Time", Abc_Clock() - clk );
232 }
233/*
234 {
235 Vec_Ptr_t * vCompletes;
236 vCompletes = Cgt_ManCompleteGates( pAig, vGatesAll, nOdcMax, fVerbose );
237 printf( "Complete gates = %d. \n", Vec_PtrSize(vCompletes) );
238 Vec_PtrFree( vCompletes );
239 }
240*/
241 return vGates;
242}
243
255Vec_Vec_t * Cgt_ManDecideArea( Aig_Man_t * pAig, Vec_Vec_t * vGatesAll, int nOdcMax, int fVerbose )
256{
257 Vec_Vec_t * vGates;
258 Vec_Ptr_t * vCompletes, * vOne;
259 Aig_Obj_t * pGate;
260 int i, k, Counter = 0;
261 abctime clk = Abc_Clock();
262 // derive and label complete gates
263 vCompletes = Cgt_ManCompleteGates( pAig, vGatesAll, nOdcMax, fVerbose );
264 // label complete gates
265 Vec_PtrForEachEntry( Aig_Obj_t *, vCompletes, pGate, i )
266 Aig_Regular(pGate)->fMarkA = 1;
267 // select only complete gates
268 vGates = Vec_VecStart( Saig_ManRegNum(pAig) );
269 Vec_VecForEachEntry( Aig_Obj_t *, vGatesAll, pGate, i, k )
270 if ( Aig_Regular(pGate)->fMarkA )
271 Vec_VecPush( vGates, i, pGate );
272 // unlabel complete gates
273 Vec_PtrForEachEntry( Aig_Obj_t *, vCompletes, pGate, i )
274 Aig_Regular(pGate)->fMarkA = 0;
275 // count the number of gated flops
276 Vec_VecForEachLevel( vGates, vOne, i )
277 {
278 Counter += (int)(Vec_PtrSize(vOne) > 0);
279// printf( "%d ", Vec_PtrSize(vOne) );
280 }
281// printf( "\n" );
282 if ( fVerbose )
283 {
284 printf( "Gating signals = %6d. Gated flops = %6d. (Total flops = %6d.)\n",
285 Vec_VecSizeSize(vGatesAll), Counter, Saig_ManRegNum(pAig) );
286 printf( "Complete gates = %6d. Gated transitions = %5.2f %%. ",
287 Vec_PtrSize(vCompletes), Cgt_ManComputeCoverage(pAig, vGates) );
288 ABC_PRT( "Time", Abc_Clock() - clk );
289 }
290 Vec_PtrFree( vCompletes );
291 return vGates;
292}
293
297
298
300
int nWords
Definition abcNpn.c:127
ABC_INT64_T abctime
Definition abc_global.h:332
#define ABC_PRT(a, t)
Definition abc_global.h:255
#define ABC_NAMESPACE_IMPL_START
#define ABC_NAMESPACE_IMPL_END
#define Aig_ObjForEachFanout(p, pObj, pFanout, iFan, i)
Definition aig.h:427
void Aig_ManIncrementTravId(Aig_Man_t *p)
DECLARATIONS ///.
Definition aigUtil.c:44
struct Aig_Obj_t_ Aig_Obj_t
Definition aig.h:51
typedefABC_NAMESPACE_HEADER_START struct Aig_Man_t_ Aig_Man_t
INCLUDES ///.
Definition aig.h:50
int Ssw_SmlCountEqual(Ssw_Sml_t *p, Aig_Obj_t *pObjLi, Aig_Obj_t *pObjLo)
Definition sswSim.c:270
int Ssw_SmlNodeCountOnesRealVec(Ssw_Sml_t *p, Vec_Ptr_t *vObjs)
Definition sswSim.c:362
int Ssw_SmlCountXorImplication(Ssw_Sml_t *p, Aig_Obj_t *pObjLi, Aig_Obj_t *pObjLo, Aig_Obj_t *pCand)
Definition sswSim.c:237
int Ssw_SmlNodeCountOnesReal(Ssw_Sml_t *p, Aig_Obj_t *pObj)
Definition sswSim.c:333
void Cgt_ManCollectFanoutPos(Aig_Man_t *pAig, Aig_Obj_t *pObj, Vec_Ptr_t *vFanout)
Definition cgtDecide.c:79
int Cgt_ManCheckGateComplete(Aig_Man_t *pAig, Vec_Vec_t *vGatesAll, Aig_Obj_t *pGate, Vec_Ptr_t *vFanout)
Definition cgtDecide.c:97
void Cgt_ManCollectFanoutPos_rec(Aig_Man_t *pAig, Aig_Obj_t *pObj, Vec_Ptr_t *vFanout)
FUNCTION DEFINITIONS ///.
Definition cgtDecide.c:52
Vec_Ptr_t * Cgt_ManCompleteGates(Aig_Man_t *pAig, Vec_Vec_t *vGatesAll, int nOdcMax, int fVerbose)
Definition cgtDecide.c:124
Vec_Vec_t * Cgt_ManDecideSimple(Aig_Man_t *pAig, Vec_Vec_t *vGatesAll, int nOdcMax, int fVerbose)
Definition cgtDecide.c:184
ABC_NAMESPACE_IMPL_START int Ssw_SmlCheckXorImplication(Ssw_Sml_t *p, Aig_Obj_t *pObjLi, Aig_Obj_t *pObjLo, Aig_Obj_t *pCand)
DECLARATIONS ///.
Definition sswSim.c:202
float Cgt_ManComputeCoverage(Aig_Man_t *pAig, Vec_Vec_t *vGates)
Definition cgtDecide.c:158
Vec_Vec_t * Cgt_ManDecideArea(Aig_Man_t *pAig, Vec_Vec_t *vGatesAll, int nOdcMax, int fVerbose)
Definition cgtDecide.c:255
Cube * p
Definition exorList.c:222
#define Saig_ManForEachLiLo(p, pObjLi, pObjLo, i)
Definition saig.h:101
struct Ssw_Sml_t_ Ssw_Sml_t
Definition ssw.h:120
Ssw_Sml_t * Ssw_SmlSimulateSeq(Aig_Man_t *pAig, int nPref, int nFrames, int nWords)
Definition sswSim.c:1248
void Ssw_SmlStop(Ssw_Sml_t *p)
Definition sswSim.c:1211
unsigned int fMarkA
Definition aig.h:79
typedefABC_NAMESPACE_HEADER_START struct Vec_Ptr_t_ Vec_Ptr_t
INCLUDES ///.
Definition vecPtr.h:42
#define Vec_PtrForEachEntry(Type, vVec, pEntry, i)
MACRO DEFINITIONS ///.
Definition vecPtr.h:55
#define Vec_VecForEachEntry(Type, vGlob, pEntry, i, k)
Definition vecVec.h:87
#define Vec_VecForEachLevel(vGlob, vVec, i)
MACRO DEFINITIONS ///.
Definition vecVec.h:55
typedefABC_NAMESPACE_HEADER_START struct Vec_Vec_t_ Vec_Vec_t
INCLUDES ///.
Definition vecVec.h:42