rewire_map.c File Reference

#include "rewire_map.h"

Include dependency graph for rewire_map.c:

Go to the source code of this file.

Functions
ABC_NAMESPACE_IMPL_START Abc_Ntk_t *	Abc_NtkFromAigPhase (Aig_Man_t *pMan)
	DECLARATIONS ///.
Abc_Ntk_t *	Abc_NtkDarAmap (Abc_Ntk_t *pNtk, Amap_Par_t *pPars)
void *	Abc_FrameReadLibGen2 ()
Vec_Int_t *	Abc_NtkWriteMiniMapping (Abc_Ntk_t *pNtk)
void	Abc_NtkPrintMiniMapping (int *pArray)
Abc_Ntk_t *	Abc_NtkFromMiniMapping (int *vMapping)
Mini_Aig_t *	Abc_MiniAigFromNtk (Abc_Ntk_t *pNtk)
void	Nf_ManSetDefaultPars (Jf_Par_t *pPars)
Gia_Man_t *	Nf_ManPerformMapping (Gia_Man_t *pGia, Jf_Par_t *pPars)
Abc_Ntk_t *	Abc_NtkFromMappedGia (Gia_Man_t *p, int fFindEnables, int fUseBuffs)
Abc_Ntk_t *	Abc_NtkFromCellMappedGia (Gia_Man_t *p, int fUseBuffs)
int	Gia_ManSimpleMapping (Gia_Man_t *p, int nBound, int Seed, int nBTLimit, int nTimeout, int fVerbose, int fKeepFile, int argc, char **argv)
Abc_Ntk_t *	Gia_ManRewirePut (Gia_Man_t *pGia)
Abc_Ntk_t *	Abc_ManRewireMapAmap (Abc_Ntk_t *pNtk)
Abc_Ntk_t *	Gia_ManRewireMapNf (Gia_Man_t *pGia)
Abc_Ntk_t *	Gia_ManRewireMapSimap (Gia_Man_t *pGia, int nBound, int nBTLimit, int nTimeout)
Vec_Int_t *	Abc_ManRewireNtkWriteMiniMapping (Abc_Ntk_t *pNtk)
Abc_Ntk_t *	Abc_ManRewireNtkFromMiniMapping (int *vMapping)
Mini_Aig_t *	Abc_ManRewireMiniAigFromNtk (Abc_Ntk_t *pNtk)

Function Documentation

Abc_FrameReadLibGen2()

void * Abc_FrameReadLibGen2 ( )

extern

Definition at line 60 of file mainFrame.c.

{ return s_GlobalFrame->pLibGen2;     } 

Abc_ManRewireMapAmap()

Abc_Ntk_t * Abc_ManRewireMapAmap

(

Abc_Ntk_t *

pNtk

)

Definition at line 46 of file rewire_map.c.

                                                 {
    Amap_Par_t Pars, *pPars = &Pars;
    Amap_ManSetDefaultParams(pPars);
    Abc_Ntk_t *pNtkMapped = Abc_NtkDarAmap(pNtk, pPars);
    if (pNtkMapped == NULL) {
        Abc_Print(-1, "Mapping has failed.\n");
        return NULL;
    }
    return pNtkMapped;
}

Here is the call graph for this function:

Here is the caller graph for this function:

Abc_ManRewireMiniAigFromNtk()

Mini_Aig_t * Abc_ManRewireMiniAigFromNtk

(

Abc_Ntk_t *

pNtk

)

Definition at line 86 of file rewire_map.c.

                                                         {
    return Abc_MiniAigFromNtk(pNtk);
}

Here is the call graph for this function:

Here is the caller graph for this function:

Abc_ManRewireNtkFromMiniMapping()

Abc_Ntk_t * Abc_ManRewireNtkFromMiniMapping

(

int *

vMapping

)

Definition at line 82 of file rewire_map.c.

                                                          {
    return Abc_NtkFromMiniMapping(vMapping);
}

Here is the call graph for this function:

Here is the caller graph for this function:

Abc_ManRewireNtkWriteMiniMapping()

Vec_Int_t * Abc_ManRewireNtkWriteMiniMapping

(

Abc_Ntk_t *

pNtk

)

Definition at line 78 of file rewire_map.c.

                                                             {
    return Abc_NtkWriteMiniMapping(pNtk);
}

Here is the call graph for this function:

Here is the caller graph for this function:

Abc_MiniAigFromNtk()

Mini_Aig_t * Abc_MiniAigFromNtk ( Abc_Ntk_t * pNtk )

extern

Definition at line 147 of file abcMini.c.

{
    Abc_Ntk_t *pNtkRes = NULL;
    Mini_Aig_t *pAig;
    if (!Abc_NtkIsStrash(pNtk)) {
        pNtk = pNtkRes = Abc_NtkStrash( pNtk, 0, 1, 0 );
        if ( pNtkRes == NULL )
        {
            printf("Strashing has failed.\n" );
            return NULL;
        }
    }
    pAig = Abc_NtkToMiniAig(pNtk);
    if (pNtkRes) Abc_NtkDelete(pNtkRes);
    return pAig;
}

Here is the call graph for this function:

Here is the caller graph for this function:

Abc_NtkDarAmap()

Abc_Ntk_t * Abc_NtkDarAmap ( Abc_Ntk_t * pNtk, Amap_Par_t * pPars )

extern

Function*************************************************************

Synopsis [Gives the current ABC network to AIG manager for processing.]

Description []

SideEffects []

SeeAlso []

Definition at line 4558 of file abcDar.c.

{
    extern Vec_Ptr_t * Amap_ManTest( Aig_Man_t * pAig, Amap_Par_t * pPars );
    Vec_Ptr_t * vMapping;
    Abc_Ntk_t * pNtkAig = NULL;
    Aig_Man_t * pMan;
    Aig_MmFlex_t * pMem;
 
    assert( Abc_NtkIsStrash(pNtk) );
    // convert to the AIG manager
    pMan = Abc_NtkToDarChoices( pNtk );
    if ( pMan == NULL )
        return NULL;
 
    // perform computation
    vMapping = Amap_ManTest( pMan, pPars );
    Aig_ManStop( pMan );
    if ( vMapping == NULL )
        return NULL;
    pMem = (Aig_MmFlex_t *)Vec_PtrPop( vMapping );
    pNtkAig = Amap_ManProduceNetwork( pNtk, vMapping );
    Aig_MmFlexStop( pMem, 0 );
    Vec_PtrFree( vMapping );
 
    // make sure everything is okay
    if ( pNtkAig && !Abc_NtkCheck( pNtkAig ) )
    {
        Abc_Print( 1, "Abc_NtkDar: The network check has failed.\n" );
        Abc_NtkDelete( pNtkAig );
        return NULL;
    }
    return pNtkAig;
}

Here is the call graph for this function:

Here is the caller graph for this function:

Abc_NtkFromAigPhase()

ABC_NAMESPACE_IMPL_START Abc_Ntk_t * Abc_NtkFromAigPhase ( Aig_Man_t * pMan )

extern

DECLARATIONS ///.

CFile****************************************************************

FileName [rewire_map.c]

SystemName [ABC: Logic synthesis and verification system.]

PackageName [Re-wiring.]

Synopsis []

Author [Jiun-Hao Chen]

Affiliation [National Taiwan University]

Date [Ver. 1.0. Started - June 20, 2005.]

Revision [

Id

rewire_map.c,v 1.00 2005/06/20 00:00:00 alanmi Exp

]

Function*************************************************************

Synopsis [Converts the network from the AIG manager into ABC.]

Description [This procedure should be called after seq sweeping, which changes the number of registers.]

SideEffects []

SeeAlso []

Definition at line 595 of file abcDar.c.

{
    Vec_Ptr_t * vNodes; 
    Abc_Ntk_t * pNtkNew;
    Abc_Obj_t * pObjNew;
    Aig_Obj_t * pObj, * pObjLo, * pObjLi;
    int i; 
    assert( pMan->nAsserts == 0 );
    // perform strashing
    pNtkNew = Abc_NtkAlloc( ABC_NTK_STRASH, ABC_FUNC_AIG, 1 );
    pNtkNew->nConstrs = pMan->nConstrs;
    pNtkNew->nBarBufs = pMan->nBarBufs;
    // duplicate the name and the spec
//    pNtkNew->pName = Extra_UtilStrsav(pMan->pName);
//    pNtkNew->pSpec = Extra_UtilStrsav(pMan->pSpec);
    Aig_ManConst1(pMan)->pData = Abc_AigConst1(pNtkNew);
    // create PIs
    Aig_ManForEachPiSeq( pMan, pObj, i )
    {
        pObjNew = Abc_NtkCreatePi( pNtkNew );
//        Abc_ObjAssignName( pObjNew, Abc_ObjName(pObjNew), NULL );
        pObj->pData = pObjNew;
    }
    // create POs
    Aig_ManForEachPoSeq( pMan, pObj, i )
    {
        pObjNew = Abc_NtkCreatePo( pNtkNew );
//        Abc_ObjAssignName( pObjNew, Abc_ObjName(pObjNew), NULL );
        pObj->pData = pObjNew;
    }
    assert( Abc_NtkCiNum(pNtkNew) == Aig_ManCiNum(pMan) - Aig_ManRegNum(pMan) );
    assert( Abc_NtkCoNum(pNtkNew) == Aig_ManCoNum(pMan) - Aig_ManRegNum(pMan) );
    // create as many latches as there are registers in the manager
    Aig_ManForEachLiLoSeq( pMan, pObjLi, pObjLo, i )
    {
        pObjNew = Abc_NtkCreateLatch( pNtkNew );
        pObjLi->pData = Abc_NtkCreateBi( pNtkNew );
        pObjLo->pData = Abc_NtkCreateBo( pNtkNew );
        Abc_ObjAddFanin( pObjNew, (Abc_Obj_t *)pObjLi->pData );
        Abc_ObjAddFanin( (Abc_Obj_t *)pObjLo->pData, pObjNew );
        Abc_LatchSetInit0( pObjNew );
//        Abc_ObjAssignName( (Abc_Obj_t *)pObjLi->pData, Abc_ObjName((Abc_Obj_t *)pObjLi->pData), NULL );
//        Abc_ObjAssignName( (Abc_Obj_t *)pObjLo->pData, Abc_ObjName((Abc_Obj_t *)pObjLo->pData), NULL );
    }
    // rebuild the AIG
    vNodes = Aig_ManDfs( pMan, 1 );
    Vec_PtrForEachEntry( Aig_Obj_t *, vNodes, pObj, i )
        if ( Aig_ObjIsBuf(pObj) )
            pObj->pData = (Abc_Obj_t *)Aig_ObjChild0Copy(pObj);
        else
            pObj->pData = Abc_AigAnd( (Abc_Aig_t *)pNtkNew->pManFunc, (Abc_Obj_t *)Aig_ObjChild0Copy(pObj), (Abc_Obj_t *)Aig_ObjChild1Copy(pObj) );
    Vec_PtrFree( vNodes );
    // connect the PO nodes
    Aig_ManForEachCo( pMan, pObj, i )
    {
        pObjNew = (Abc_Obj_t *)Aig_ObjChild0Copy(pObj);
        Abc_ObjAddFanin( Abc_NtkCo(pNtkNew, i), pObjNew );
    }
 
    Abc_NtkAddDummyPiNames( pNtkNew );
    Abc_NtkAddDummyPoNames( pNtkNew );
    Abc_NtkAddDummyBoxNames( pNtkNew );
 
    // check the resulting AIG
    if ( !Abc_NtkCheck( pNtkNew ) )
        Abc_Print( 1, "Abc_NtkFromAigPhase(): Network check has failed.\n" );
    return pNtkNew;
}

Here is the caller graph for this function:

Abc_NtkFromCellMappedGia()

Abc_Ntk_t * Abc_NtkFromCellMappedGia ( Gia_Man_t * p, int fUseBuffs )

extern

Definition at line 967 of file abcDar.c.

{
    int fFixDrivers = 1;
    int fVerbose = 0;
    Abc_Ntk_t * pNtkNew;
    Vec_Int_t * vCopyLits;
    Abc_Obj_t * pObjNew, * pObjNewLi, * pObjNewLo;
    Gia_Obj_t * pObj, * pObjLi, * pObjLo;
    int i, k, iLit, iFanLit, nCells, fNeedConst[2] = {0}; 
    Mio_Cell2_t * pCells = Mio_CollectRootsNewDefault2( 6, &nCells, 0 );
    assert( Gia_ManHasCellMapping(p) );
    // start network
    pNtkNew = Abc_NtkAlloc( ABC_NTK_LOGIC, ABC_FUNC_MAP, 1 );
    pNtkNew->pName = Extra_UtilStrsav(p->pName);
    pNtkNew->pSpec = Extra_UtilStrsav(p->pSpec);
    assert( pNtkNew->pManFunc == Abc_FrameReadLibGen() );
    vCopyLits = Vec_IntStartFull( 2*Gia_ManObjNum(p) );
    // create PIs
    Gia_ManForEachPi( p, pObj, i )
        Abc_NtkFromCellWrite( vCopyLits, Gia_ObjId(p, pObj), 0, Abc_ObjId( Abc_NtkCreatePi( pNtkNew ) ) );
    // create POs
    Gia_ManForEachPo( p, pObj, i )
        Abc_NtkFromCellWrite( vCopyLits, Gia_ObjId(p, pObj), 0, Abc_ObjId( Abc_NtkCreatePo( pNtkNew ) ) );
    // create as many latches as there are registers in the manager
    Gia_ManForEachRiRo( p, pObjLi, pObjLo, i )
    {
        pObjNew = Abc_NtkCreateLatch( pNtkNew );
        pObjNewLi = Abc_NtkCreateBi( pNtkNew );
        pObjNewLo = Abc_NtkCreateBo( pNtkNew );
        Abc_ObjAddFanin( pObjNew, pObjNewLi );
        Abc_ObjAddFanin( pObjNewLo, pObjNew );
//        pObjLi->Value = Abc_ObjId( pObjNewLi );
//        pObjLo->Value = Abc_ObjId( pObjNewLo );
        Abc_NtkFromCellWrite( vCopyLits, Gia_ObjId(p, pObjLi), 0, Abc_ObjId( pObjNewLi ) );
        Abc_NtkFromCellWrite( vCopyLits, Gia_ObjId(p, pObjLo), 0, Abc_ObjId( pObjNewLo ) );
        Abc_LatchSetInit0( pObjNew );
    }
 
    // create constants
    Gia_ManForEachCo( p, pObj, i )
        if ( Gia_ObjFaninId0p(p, pObj) == 0 )
            fNeedConst[Gia_ObjFaninC0(pObj)] = 1;
    Gia_ManForEachBuf( p, pObj, i )
        if ( Gia_ObjFaninId0p(p, pObj) == 0 )
            fNeedConst[Gia_ObjFaninC0(pObj)] = 1;
    if ( fNeedConst[0] )
        Abc_NtkFromCellWrite( vCopyLits, 0, 0, Abc_ObjId(Abc_NtkCreateNodeConst0(pNtkNew)) );
    if ( fNeedConst[1] )
        Abc_NtkFromCellWrite( vCopyLits, 0, 1, Abc_ObjId(Abc_NtkCreateNodeConst1(pNtkNew)) );
 
    // rebuild the AIG
    Gia_ManForEachCell( p, iLit )
    {
        int fSkip = 0;
        if ( Gia_ObjIsCellBuf(p, iLit) )
        {
            assert( !Abc_LitIsCompl(iLit) );
            // build buffer
            pObjNew = Abc_NtkCreateNode( pNtkNew );
            iFanLit = Gia_ObjFaninLit0p( p, Gia_ManObj(p, Abc_Lit2Var(iLit)) );
            Abc_ObjAddFanin( pObjNew, Abc_NtkFromCellRead(pNtkNew, vCopyLits, Abc_Lit2Var(iFanLit), Abc_LitIsCompl(iFanLit)) );
            pObjNew->pData = NULL; // barrier buffer
            assert( Abc_ObjIsBarBuf(pObjNew) );
            pNtkNew->nBarBufs2++;
        }
        else if ( Gia_ObjIsCellInv(p, iLit) )
        {
            int iLitNot = Abc_LitNot(iLit);
            if ( !Abc_LitIsCompl(iLit) ) // positive phase
            {
                // build negative phase
                assert( Vec_IntEntry(vCopyLits, iLitNot) == -1 );
                assert( Gia_ObjCellId(p, iLitNot) > 0 );
                pObjNew = Abc_NtkCreateNode( pNtkNew );
                Gia_CellForEachFanin( p, iLitNot, iFanLit, k )
                    Abc_ObjAddFanin( pObjNew, Abc_NtkFromCellRead(pNtkNew, vCopyLits, Abc_Lit2Var(iFanLit), Abc_LitIsCompl(iFanLit)) );
                pObjNew->pData = Mio_LibraryReadGateByName( (Mio_Library_t *)pNtkNew->pManFunc, pCells[Gia_ObjCellId(p, iLitNot)].pName, NULL );
                Abc_NtkFromCellWrite( vCopyLits, Abc_Lit2Var(iLitNot), Abc_LitIsCompl(iLitNot), Abc_ObjId(pObjNew) );
                fSkip = 1;
            }
            else // negative phase
            {
                // positive phase is available
                assert( Vec_IntEntry(vCopyLits, iLitNot) != -1 );
            }
            // build inverter
            pObjNew = Abc_NtkCreateNode( pNtkNew );
            Abc_ObjAddFanin( pObjNew, Abc_NtkFromCellRead(pNtkNew, vCopyLits, Abc_Lit2Var(iLit), Abc_LitIsCompl(iLitNot)) );
            pObjNew->pData = Mio_LibraryReadGateByName( (Mio_Library_t *)pNtkNew->pManFunc, pCells[3].pName, NULL );
        }
        else
        {
            assert( Gia_ObjCellId(p, iLit) >= 0 );
            pObjNew = Abc_NtkCreateNode( pNtkNew );
            Gia_CellForEachFanin( p, iLit, iFanLit, k )
                Abc_ObjAddFanin( pObjNew, Abc_NtkFromCellRead(pNtkNew, vCopyLits, Abc_Lit2Var(iFanLit), Abc_LitIsCompl(iFanLit)) );
            pObjNew->pData = Mio_LibraryReadGateByName( (Mio_Library_t *)pNtkNew->pManFunc, pCells[Gia_ObjCellId(p, iLit)].pName, NULL );
        }
        assert( Vec_IntEntry(vCopyLits, iLit) == -1 );
        Abc_NtkFromCellWrite( vCopyLits, Abc_Lit2Var(iLit), Abc_LitIsCompl(iLit), Abc_ObjId(pObjNew) );
        // skip next
        iLit += fSkip;
    }
 
    // connect the PO nodes
    Gia_ManForEachCo( p, pObj, i )
    {
        pObjNew = Abc_NtkFromCellRead( pNtkNew, vCopyLits, Gia_ObjFaninId0p(p, pObj), Gia_ObjFaninC0(pObj) );
        Abc_ObjAddFanin( Abc_NtkCo(pNtkNew, i), pObjNew );
    }
    // create names
    Abc_NtkAddDummyPiNames( pNtkNew );
    Abc_NtkAddDummyPoNames( pNtkNew );
    Abc_NtkAddDummyBoxNames( pNtkNew );
 
    // decouple the PO driver nodes to reduce the number of levels
    if ( fFixDrivers )
    {
        int nDupGates = Abc_NtkLogicMakeSimpleCos( pNtkNew, !fUseBuffs );
        if ( fVerbose && nDupGates && !Abc_FrameReadFlag("silentmode") )
        {
            if ( fUseBuffs )
                printf( "Added %d buffers/inverters to decouple the CO drivers.\n", nDupGates );
            else
                printf( "Duplicated %d gates to decouple the CO drivers.\n", nDupGates );
        }
    }
 
    assert( Gia_ManPiNum(p) == Abc_NtkPiNum(pNtkNew) );
    assert( Gia_ManPoNum(p) == Abc_NtkPoNum(pNtkNew) );
    assert( Gia_ManRegNum(p) == Abc_NtkLatchNum(pNtkNew) );
    Vec_IntFree( vCopyLits );
    ABC_FREE( pCells );
 
    // check the resulting AIG
    if ( !Abc_NtkCheck( pNtkNew ) )
        Abc_Print( 1, "Abc_NtkFromMappedGia(): Network check has failed.\n" );
    return pNtkNew;
}

Here is the call graph for this function:

Here is the caller graph for this function:

Abc_NtkFromMappedGia()

Abc_Ntk_t * Abc_NtkFromMappedGia ( Gia_Man_t * p, int fFindEnables, int fUseBuffs )

extern

Definition at line 768 of file abcDar.c.

{
    int fVerbose = 0;
    int fDuplicate = 0;
    Abc_Ntk_t * pNtkNew;
    Abc_Obj_t * pObjNew, * pObjNewLi, * pObjNewLo, * pConst0 = NULL;
    Gia_Obj_t * pObj, * pObjLi, * pObjLo;
    Vec_Ptr_t * vReflect;
    int i, k, iFan, nDupGates, nCountMux = 0; 
    assert( Gia_ManHasMapping(p) || p->pMuxes || fFindEnables );
    assert( !fFindEnables || !p->pMuxes );
    pNtkNew = Abc_NtkAlloc( ABC_NTK_LOGIC, Gia_ManHasMapping(p) ? ABC_FUNC_AIG : ABC_FUNC_SOP, 1 );
    // duplicate the name and the spec
    pNtkNew->pName = Extra_UtilStrsav(p->pName);
    pNtkNew->pSpec = Extra_UtilStrsav(p->pSpec);
    Gia_ManFillValue( p );
    // create constant
    pConst0 = Abc_NtkCreateNodeConst0( pNtkNew );
    Gia_ManConst0(p)->Value = Abc_ObjId(pConst0);
    // create PIs
    Gia_ManForEachPi( p, pObj, i )
        pObj->Value = Abc_ObjId( Abc_NtkCreatePi( pNtkNew ) );
    // create POs
    Gia_ManForEachPo( p, pObj, i )
        pObj->Value = Abc_ObjId( Abc_NtkCreatePo( pNtkNew ) );
    // create as many latches as there are registers in the manager
    Gia_ManForEachRiRo( p, pObjLi, pObjLo, i )
    {
        pObjNew = Abc_NtkCreateLatch( pNtkNew );
        pObjNewLi = Abc_NtkCreateBi( pNtkNew );
        pObjNewLo = Abc_NtkCreateBo( pNtkNew );
        Abc_ObjAddFanin( pObjNew, pObjNewLi );
        Abc_ObjAddFanin( pObjNewLo, pObjNew );
        pObjLi->Value = Abc_ObjId( pObjNewLi );
        pObjLo->Value = Abc_ObjId( pObjNewLo );
        Abc_LatchSetInit0( pObjNew );
    }
    // rebuild the AIG
    if ( fFindEnables )
    {
        Gia_ManForEachCo( p, pObj, i )
        {
            pObjNew = NULL;
            if ( Gia_ObjIsRi(p, pObj) && Gia_ObjIsMuxType(Gia_ObjFanin0(pObj)) )
            {
                int iObjRo = Gia_ObjRiToRoId( p, Gia_ObjId(p, pObj) );
                int iLitE, iLitT, iCtrl = Gia_ObjRecognizeMuxLits( p, Gia_ObjFanin0(pObj), &iLitT, &iLitE );
                iLitE = Abc_LitNotCond( iLitE, Gia_ObjFaninC0(pObj) );
                iLitT = Abc_LitNotCond( iLitT, Gia_ObjFaninC0(pObj) );
                if ( Abc_Lit2Var(iLitT) == iObjRo )
                {
                    int iTemp = iLitE;
                    iLitE = iLitT;
                    iLitT = iTemp;
                    iCtrl = Abc_LitNot( iCtrl );
                }
                if ( Abc_Lit2Var(iLitE) == iObjRo )
                {
                    Abc_Obj_t * pObjCtrl  = Abc_NtkFromMappedGia_rec( pNtkNew, p, Abc_Lit2Var(iCtrl), Abc_LitIsCompl(iCtrl) );
                    Abc_Obj_t * pObjNodeT = Abc_NtkFromMappedGia_rec( pNtkNew, p, Abc_Lit2Var(iLitT), Abc_LitIsCompl(iLitT) );
                    Abc_Obj_t * pObjNodeE = Abc_NtkFromMappedGia_rec( pNtkNew, p, Abc_Lit2Var(iLitE), Abc_LitIsCompl(iLitE) );
                    pObjNew = Abc_NtkCreateNode( pNtkNew );
                    Abc_ObjAddFanin( pObjNew, pObjCtrl );
                    Abc_ObjAddFanin( pObjNew, pObjNodeT );
                    Abc_ObjAddFanin( pObjNew, pObjNodeE );
                    pObjNew->pData = Abc_SopCreateMux( (Mem_Flex_t *)pNtkNew->pManFunc );
                    nCountMux++;
                }
            }
            if ( pObjNew == NULL )
                pObjNew = Abc_NtkFromMappedGia_rec( pNtkNew, p, Gia_ObjFaninId0p(p, pObj), Gia_ObjFaninC0(pObj) );
            Abc_ObjAddFanin( Abc_NtkCo(pNtkNew, i), pObjNew );
        }
    }
    else if ( p->pMuxes )
    {
        Gia_ManForEachAnd( p, pObj, i )
        {
            pObjNew = Abc_NtkCreateNode( pNtkNew );
            if ( Gia_ObjIsMuxId(p, i) )
            {
                Abc_ObjAddFanin( pObjNew, Abc_NtkObj(pNtkNew, Gia_ObjValue(Gia_ObjFanin2(p, pObj))) );
                Abc_ObjAddFanin( pObjNew, Abc_NtkObj(pNtkNew, Gia_ObjValue(Gia_ObjFanin1(pObj))) );
                Abc_ObjAddFanin( pObjNew, Abc_NtkObj(pNtkNew, Gia_ObjValue(Gia_ObjFanin0(pObj))) );
                pObjNew->pData = Abc_SopCreateMux( (Mem_Flex_t *)pNtkNew->pManFunc );
                if ( Gia_ObjFaninC2(p, pObj) )  Abc_SopComplementVar( (char *)pObjNew->pData, 0 );
                if ( Gia_ObjFaninC1(pObj) )     Abc_SopComplementVar( (char *)pObjNew->pData, 1 );
                if ( Gia_ObjFaninC0(pObj) )     Abc_SopComplementVar( (char *)pObjNew->pData, 2 );
            }
            else if ( Gia_ObjIsXor(pObj) )
            {
                Abc_ObjAddFanin( pObjNew, Abc_NtkObj(pNtkNew, Gia_ObjValue(Gia_ObjFanin0(pObj))) );
                Abc_ObjAddFanin( pObjNew, Abc_NtkObj(pNtkNew, Gia_ObjValue(Gia_ObjFanin1(pObj))) );
                pObjNew->pData = Abc_SopCreateXor( (Mem_Flex_t *)pNtkNew->pManFunc, 2 );
                if ( Gia_ObjFaninC0(pObj) )  Abc_SopComplementVar( (char *)pObjNew->pData, 0 );
                if ( Gia_ObjFaninC1(pObj) )  Abc_SopComplementVar( (char *)pObjNew->pData, 1 );
            }
            else 
            {
                Abc_ObjAddFanin( pObjNew, Abc_NtkObj(pNtkNew, Gia_ObjValue(Gia_ObjFanin0(pObj))) );
                Abc_ObjAddFanin( pObjNew, Abc_NtkObj(pNtkNew, Gia_ObjValue(Gia_ObjFanin1(pObj))) );
                pObjNew->pData = Abc_SopCreateAnd( (Mem_Flex_t *)pNtkNew->pManFunc, 2, NULL );
                if ( Gia_ObjFaninC0(pObj) )  Abc_SopComplementVar( (char *)pObjNew->pData, 0 );
                if ( Gia_ObjFaninC1(pObj) )  Abc_SopComplementVar( (char *)pObjNew->pData, 1 );
            }
            pObj->Value = Abc_ObjId( pObjNew );
        }
    }
    else
    {
        vReflect = Vec_PtrStart( Gia_ManObjNum(p) );
        Gia_ManForEachLut( p, i )
        {
            pObj = Gia_ManObj(p, i);
            assert( pObj->Value == ~0 );
            if ( Gia_ObjLutSize(p, i) == 0 )
            {
                pObj->Value = Abc_ObjId(pConst0);
                continue;
            }
            pObjNew = Abc_NtkCreateNode( pNtkNew );
            Gia_LutForEachFanin( p, i, iFan, k )
                Abc_ObjAddFanin( pObjNew, Abc_NtkObj(pNtkNew, Gia_ObjValue(Gia_ManObj(p, iFan))) );
            pObjNew->pData = Abc_ObjHopFromGia( (Hop_Man_t *)pNtkNew->pManFunc, p, i, vReflect );
            pObjNew->fPersist = Gia_ObjLutIsMux(p, i) && Gia_ObjLutSize(p, i) == 3;
            pObj->Value = Abc_ObjId( pObjNew );
        }
        Vec_PtrFree( vReflect );
    }
    //if ( fFindEnables )
    //    printf( "Extracted %d flop enable signals.\n", nCountMux );
    // connect the PO nodes
    if ( !fFindEnables )
    Gia_ManForEachCo( p, pObj, i )
    {
        pObjNew = Abc_NtkObj( pNtkNew, Gia_ObjValue(Gia_ObjFanin0(pObj)) );
        Abc_ObjAddFanin( Abc_NtkCo(pNtkNew, i), Abc_ObjNotCond( pObjNew, Gia_ObjFaninC0(pObj) ) );
    }
    // create names
    Abc_NtkAddDummyPiNames( pNtkNew );
    Abc_NtkAddDummyPoNames( pNtkNew );
    Abc_NtkAddDummyBoxNames( pNtkNew );
 
    // decouple the PO driver nodes to reduce the number of levels
    nDupGates = Abc_NtkLogicMakeSimpleCos( pNtkNew, !fUseBuffs );
    if ( fVerbose && nDupGates && !Abc_FrameReadFlag("silentmode") )
    {
        if ( !fDuplicate )
            printf( "Added %d buffers/inverters to decouple the CO drivers.\n", nDupGates );
        else
            printf( "Duplicated %d gates to decouple the CO drivers.\n", nDupGates );
    }
    // remove const node if it is not used
    if ( !Abc_ObjIsNone(pConst0) && Abc_ObjFanoutNum(pConst0) == 0 )
        Abc_NtkDeleteObj( pConst0 );
 
    assert( Gia_ManPiNum(p) == Abc_NtkPiNum(pNtkNew) );
    assert( Gia_ManPoNum(p) == Abc_NtkPoNum(pNtkNew) );
    assert( Gia_ManRegNum(p) == Abc_NtkLatchNum(pNtkNew) );
 
    // check the resulting AIG
    if ( !Abc_NtkCheck( pNtkNew ) )
        Abc_Print( 1, "Abc_NtkFromMappedGia(): Network check has failed.\n" );
    return pNtkNew;
}

Here is the call graph for this function:

Abc_NtkFromMiniMapping()

Abc_Ntk_t * Abc_NtkFromMiniMapping ( int * pArray )

extern

Function*************************************************************

Synopsis [Build mapped network from the mini-mapped format.]

Description []

SideEffects []

SeeAlso []

Definition at line 907 of file abcMap.c.

{
    if ( !pArray ) {
        printf("Mapping is not available.\n");
        return NULL;
    }
    Mio_Library_t * pLib = (Mio_Library_t *)Abc_FrameReadLibGen();
    if ( !pLib ) {
        printf("Library is not available.\n");
        return NULL;
    }
    Abc_Ntk_t *pNtkMapped = Abc_NtkAlloc( ABC_NTK_LOGIC, ABC_FUNC_MAP, 1 );
    pNtkMapped->pName = Extra_UtilStrsav( "mapped" );
    pNtkMapped->pManFunc = pLib;
    int nCis, nCos, nNodes, nFlops;
    int i, k, nLeaves, Pos = 4;
    char * pBuffer, * pName;
    Mio_Gate_t *pGate;
    Abc_Obj_t * pObj;
    nCis = pArray[0];
    nCos = pArray[1];
    nNodes = pArray[2];
    nFlops = pArray[3];
    // create pis
    for ( i = 0; i < nCis-nFlops; i++ )
        Abc_NtkCreatePi( pNtkMapped );
    // create nodes
    for ( i = 0; i < nNodes; i++ )
        Abc_NtkCreateNode( pNtkMapped );
    // create pos
    for ( i = 0; i < nCos-nFlops; i++ )
        Abc_NtkCreatePo( pNtkMapped );
    // create flops
    for ( i = 0; i < nFlops; i++ )
        Abc_NtkAddLatch( pNtkMapped, NULL, ABC_INIT_ZERO );
    // connect nodes
    for ( i = 0; i < nNodes; i++ )
    {
        nLeaves = pArray[Pos++];
        for ( k = 0; k < nLeaves; k++ )
            Abc_ObjAddFanin( Abc_NtkObj( pNtkMapped, nCis + i + 1 ), Abc_NtkObj( pNtkMapped, pArray[Pos++] + 1 ) );
    }
    for ( i = 0; i < nCos; i++ )
        Abc_ObjAddFanin( Abc_NtkCo( pNtkMapped, i ), Abc_NtkObj( pNtkMapped, pArray[Pos++] + 1 ) );
 
    pBuffer = (char *)(pArray + Pos);
    for ( i = 0; i < nNodes; i++ )
    {
        pName = pBuffer;
        pBuffer += strlen(pName) + 1;
        pGate = Mio_LibraryReadGateByName( pLib, pName, NULL );
        Abc_NtkObj( pNtkMapped, nCis + i + 1 )->pData = pGate;
    }
 
    assert( Abc_NtkCiNum(pNtkMapped) == nCis );
    Abc_NtkForEachCi( pNtkMapped, pObj, i ) {
        pName = pBuffer;
        pBuffer += strlen(pName) + 1;
        Abc_ObjAssignName( pObj, pName, NULL );
    }
    assert( Abc_NtkCoNum(pNtkMapped) == nCos );
    Abc_NtkForEachCo( pNtkMapped, pObj, i ) {
        pName = pBuffer;
        pBuffer += strlen(pName) + 1;
        Abc_ObjAssignName( pObj, pName, NULL );
    }
 
    if ( !Abc_NtkCheck( pNtkMapped ) ) {
        fprintf( stdout, "Abc_NtkFromMiniMapping(): Network check has failed.\n" );
    }
 
    return pNtkMapped;
}

Here is the call graph for this function:

Here is the caller graph for this function:

Abc_NtkPrintMiniMapping()

void Abc_NtkPrintMiniMapping ( int * pArray )

extern

Function*************************************************************

Synopsis [Prints mapped network represented in mini-mapped format.]

Description []

SideEffects []

SeeAlso []

Definition at line 1030 of file abcMap.c.

{
    int nCis, nCos, nNodes, nFlops;
    int i, k, nLeaves, Pos = 4;
    char * pBuffer, * pName;
    nCis = pArray[0];
    nCos = pArray[1];
    nNodes = pArray[2];
    nFlops = pArray[3];
    printf( "Mapped network has %d CIs, %d COs, %d gates, and %d flops.\n", nCis, nCos, nNodes, nFlops );
    printf( "The first %d object IDs (from 0 to %d) are reserved for the CIs.\n", nCis, nCis - 1 );
    for ( i = 0; i < nNodes; i++ )
    {
        nLeaves = pArray[Pos++];
        printf( "Node %d has %d fanins {", nCis + i, nLeaves );
        for ( k = 0; k < nLeaves; k++ )
            printf( " %d", pArray[Pos++] );
        printf( " }\n" );
    }
    for ( i = 0; i < nCos; i++ )
        printf( "CO %d is driven by node %d\n", i, pArray[Pos++] );
    pBuffer = (char *)(pArray + Pos);
    for ( i = 0; i < nNodes; i++ )
    {
        pName = pBuffer;
        pBuffer += strlen(pName) + 1;
        printf( "Node %d has gate \"%s\"\n", nCis + i, pName );
    }
    for ( i = 0; i < nCis; i++ )
    {
        pName = pBuffer;
        pBuffer += strlen(pName) + 1;
        printf( "CI %d has name \"%s\"\n", i, pName );
    }
    for ( i = 0; i < nCos; i++ )
    {
        pName = pBuffer;
        pBuffer += strlen(pName) + 1;
        printf( "CO %d has name \"%s\"\n", i, pName );
    }
}

Here is the call graph for this function:

Here is the caller graph for this function:

Abc_NtkWriteMiniMapping()

Vec_Int_t * Abc_NtkWriteMiniMapping ( Abc_Ntk_t * pNtk )

extern

Function*************************************************************

Synopsis [Dumps mapped network in the mini-mapped format.]

Description []

SideEffects []

SeeAlso []

Definition at line 834 of file abcMap.c.

{
    Vec_Ptr_t * vNodes;
    Vec_Int_t * vMapping;
    Vec_Str_t * vGates;
    Abc_Obj_t * pObj, * pFanin;
    int i, k, nNodes, nFanins, nExtra, * pArray;
    assert( Abc_NtkHasMapping(pNtk) );
    // collect nodes in the DFS order
    vNodes = Abc_NtkDfs( pNtk, 0 );
    // assign unique numbers
    nNodes = nFanins = 0;
    Abc_NtkForEachCi( pNtk, pObj, i )
        pObj->iTemp = nNodes++;
    Vec_PtrForEachEntry( Abc_Obj_t *, vNodes, pObj, i )
        pObj->iTemp = nNodes++, nFanins += Abc_ObjFaninNum(pObj);
    // allocate attay to store mapping (4 counters + fanins for each node + PO drivers + gate names)
    vMapping = Vec_IntAlloc( 4 + Abc_NtkNodeNum(pNtk) + nFanins + Abc_NtkCoNum(pNtk) + 10000 );
    // write the numbers of CI/CO/Node/FF
    Vec_IntPush( vMapping, Abc_NtkCiNum(pNtk) );
    Vec_IntPush( vMapping, Abc_NtkCoNum(pNtk) );
    Vec_IntPush( vMapping, Vec_PtrSize(vNodes) );
    Vec_IntPush( vMapping, Abc_NtkLatchNum(pNtk) );
    // write the nodes
    vGates = Vec_StrAlloc( 10000 );
    Vec_PtrForEachEntry( Abc_Obj_t *, vNodes, pObj, i )
    {
        Vec_IntPush( vMapping, Abc_ObjFaninNum(pObj) );
        Abc_ObjForEachFanin( pObj, pFanin, k )
            Vec_IntPush( vMapping, pFanin->iTemp );
        // remember this gate (to be added to the mapping later)
        Vec_StrPrintStr( vGates, Mio_GateReadName((Mio_Gate_t *)pObj->pData) );
        Vec_StrPush( vGates, '\0' );
    }
    // write the COs literals
    Abc_NtkForEachCo( pNtk, pObj, i )
        Vec_IntPush( vMapping, Abc_ObjFanin0(pObj)->iTemp );
    // write signal names
    Abc_NtkForEachCi( pNtk, pObj, i ) {
        Vec_StrPrintStr( vGates, Abc_ObjName(pObj) );        
        Vec_StrPush( vGates, '\0' );
    }
    Abc_NtkForEachCo( pNtk, pObj, i ) {
        Vec_StrPrintStr( vGates, Abc_ObjName(pObj) );
        Vec_StrPush( vGates, '\0' );
    }
    // finish off the array
    nExtra = 4 - Vec_StrSize(vGates) % 4;
    for ( i = 0; i < nExtra; i++ )
        Vec_StrPush( vGates, '\0' );
    // add gates to the array
    assert( Vec_StrSize(vGates) % 4 == 0 );
    nExtra = Vec_StrSize(vGates) / 4;
    pArray = (int *)Vec_StrArray(vGates);
    for ( i = 0; i < nExtra; i++ )
        Vec_IntPush( vMapping, pArray[i] );
    // cleanup and return
    Vec_PtrFree( vNodes );
    Vec_StrFree( vGates );
    return vMapping;
}

Here is the call graph for this function:

Here is the caller graph for this function:

Gia_ManRewireMapNf()

Abc_Ntk_t * Gia_ManRewireMapNf

(

Gia_Man_t *

pGia

)

Definition at line 57 of file rewire_map.c.

                                               {
    Jf_Par_t Pars, * pPars = &Pars;
    Nf_ManSetDefaultPars( pPars );
    Gia_Man_t *pGiaNew = Nf_ManPerformMapping(pGia, pPars);
    if (pGiaNew == NULL) {
        Abc_Print(-1, "Mapping has failed.\n");
        return NULL;
    }
    Abc_Ntk_t *pNtkMapped = Abc_NtkFromCellMappedGia(pGiaNew, 0);
    return pNtkMapped;
}

Here is the call graph for this function:

Here is the caller graph for this function:

Gia_ManRewireMapSimap()

Abc_Ntk_t * Gia_ManRewireMapSimap	(	Gia_Man_t *	pGia,
		int	nBound,
		int	nBTLimit,
		int	nTimeout )

Definition at line 69 of file rewire_map.c.

                                                                                          {
    if (!Gia_ManSimpleMapping(pGia, nBound, 0, nBTLimit, nTimeout, 0, 0, 0, NULL)) {
        // Abc_Print(-1, "Mapping has failed.\n");
        return NULL;
    }
    Abc_Ntk_t *pNtkMapped = Abc_NtkFromCellMappedGia(pGia, 0);
    return pNtkMapped;
}

Here is the call graph for this function:

Here is the caller graph for this function:

Gia_ManRewirePut()

Abc_Ntk_t * Gia_ManRewirePut

(

Gia_Man_t *

pGia

)

CFile****************************************************************

FileName [rewire_map.h]

SystemName [ABC: Logic synthesis and verification system.]

PackageName [Re-wiring.]

Synopsis []

Author [Jiun-Hao Chen]

Affiliation [National Taiwan University]

Date [Ver. 1.0. Started - June 20, 2005.]

Revision [

Id

rewire_map.h,v 1.00 2005/06/20 00:00:00 alanmi Exp

]

Definition at line 38 of file rewire_map.c.

                                             {
    Aig_Man_t *pMan = Gia_ManToAig(pGia, 0);
    Abc_Ntk_t *pNtk = Abc_NtkFromAigPhase(pMan);
    Abc_NtkSetName(pNtk, Abc_UtilStrsav(Gia_ManName(pGia)));
    Aig_ManStop(pMan);
    return pNtk;
}

Here is the call graph for this function:

Here is the caller graph for this function:

Gia_ManSimpleMapping()

int Gia_ManSimpleMapping ( Gia_Man_t * p, int nBound, int Seed, int nBTLimit, int nTimeout, int fVerbose, int fKeepFile, int argc, char ** argv )

extern

Definition at line 1572 of file giaSatLut.c.

{
    abctime clkStart = Abc_Clock();
    srand(time(NULL));
    int Status, Rand = ((((unsigned)rand()) << 12) ^ ((unsigned)rand())) & 0xFFFFFF;
    char pFileNameI[32]; sprintf( pFileNameI, "_%06x_.cnf", Rand ); 
    char pFileNameO[32]; sprintf( pFileNameO, "_%06x_.out", Rand ); 
    if ( nBound == 0 ) 
        nBound = 5 * Gia_ManAndNum(p);
    Vec_Str_t * vStr = Gia_ManSimpleCnf( p, nBound/2 );
    int nVars = 7*(Gia_ManObjNum(p)-Gia_ManCoNum(p));
    if ( !Gia_ManDumpCnf(pFileNameI, vStr, nVars) ) {
        Vec_StrFree( vStr );
        return 0;
    }
    if ( fVerbose )
        printf( "SAT variables = %d. SAT clauses = %d. Cardinality bound = %d. Conflict limit = %d. Timeout = %d.\n", 
            nVars, Vec_StrCountEntry(vStr, '\n'), nBound, nBTLimit, nTimeout );
    Vec_Int_t * vRes = Gia_RunKadical( pFileNameI, pFileNameO, Seed, nBTLimit, nTimeout, fVerbose, &Status );
    unlink( pFileNameI );
    //unlink( pFileNameO );
    if ( fKeepFile ) Gia_ManDumpCnf2( vStr, nVars, argc, argv, Abc_Clock() - clkStart, Status );
    Vec_StrFree( vStr );
    if ( vRes == NULL )
        return 0;
    Vec_IntFreeP( &p->vCellMapping );
    assert( p->vCellMapping == NULL );
    Vec_IntDrop( vRes, 0 );
    if ( fVerbose ) Gia_ManSimplePrintMapping( vRes, Gia_ManCiNum(p) );
    p->vCellMapping = Gia_ManDeriveSimpleMapping( p, vRes );
    Vec_IntFree( vRes );
    if ( fVerbose ) Abc_PrintTime( 0, "Total time", Abc_Clock() - clkStart );
    return 1;
}

Here is the call graph for this function:

Here is the caller graph for this function:

Nf_ManPerformMapping()

Gia_Man_t * Nf_ManPerformMapping ( Gia_Man_t * pGia, Jf_Par_t * pPars )

extern

Definition at line 2734 of file giaNf.c.

{
    Gia_Man_t * pNew;
    if ( p->pManTime && Tim_ManBoxNum((Tim_Man_t*)p->pManTime) && Gia_ManIsNormalized(p) )
    {
        pNew = Gia_ManDupUnnormalize( p );
        if ( pNew == NULL )
            return NULL;
        Gia_ManTransferTiming( pNew, p );
        p = pNew;
        // mapping
        pNew = Nf_ManPerformMappingInt( p, pPars );
        if ( pNew != p )
        {
            Gia_ManTransferTiming( pNew, p );
            Gia_ManStop( p );
        }
        // normalize
        pNew = Gia_ManDupNormalize( p = pNew, 0 );
        Gia_ManTransferCellMapping( pNew, p );
        Gia_ManTransferTiming( pNew, p );
        Gia_ManStop( p );
        assert( Gia_ManIsNormalized(pNew) );
    }
    else 
    {
        pNew = Nf_ManPerformMappingInt( p, pPars );
        Gia_ManTransferTiming( pNew, p );
        //Gia_ManCellMappingVerify( pNew );
        // remove choices after mapping
        ABC_FREE( pNew->pReprs );
        ABC_FREE( pNew->pNexts );        
    }
    //pNew->MappedDelay = (int)((If_Par_t *)pp)->FinalDelay;
    //pNew->MappedArea  = (int)((If_Par_t *)pp)->FinalArea;
    return pNew;
}

Here is the call graph for this function:

Here is the caller graph for this function:

Nf_ManSetDefaultPars()

void Nf_ManSetDefaultPars ( Jf_Par_t * pPars )

extern

Function*************************************************************

Synopsis [Technology mappping.]

Description []

SideEffects []

SeeAlso []

Definition at line 2527 of file giaNf.c.

{
    memset( pPars, 0, sizeof(Jf_Par_t) );
    pPars->nLutSize     =  6;
    pPars->nCutNum      = 16;
    pPars->nProcNum     =  0;
    pPars->nRounds      =  4;
    pPars->nRoundsEla   =  2;
    pPars->nRelaxRatio  =  0;
    pPars->nCoarseLimit =  3;
    pPars->nAreaTuner   =  0;
    pPars->nReqTimeFlex =  0;
    pPars->nVerbLimit   =  5;
    pPars->DelayTarget  = -1;
    pPars->fAreaOnly    =  0;
    pPars->fPinPerm     =  0;
    pPars->fPinQuick    =  0;
    pPars->fPinFilter   =  0;
    pPars->fOptEdge     =  1; 
    pPars->fCoarsen     =  0;
    pPars->fCutMin      =  1;
    pPars->fGenCnf      =  0;
    pPars->fPureAig     =  0;
    pPars->fVerbose     =  0;
    pPars->fVeryVerbose =  0;
    pPars->nLutSizeMax  =  NF_LEAF_MAX;
    pPars->nCutNumMax   =  NF_CUT_MAX;
    pPars->MapDelayTarget = 0;
}

Here is the call graph for this function:

Here is the caller graph for this function: